Design of a 3.3 V 12 bit CMOS D/A converter with a high linearity

Abstract

This paper describes a 3.3 V, 65 MHz 12 bit CMOS current-mode DAC designed with a 8 MSB current matrix stage and a 4 LSB binary weighting stage. The linearity errors caused by a voltage drop of the ground line and a threshold voltage mismatch of transistors have been reduced by the symmetrical routing method with a ground line and the tree structure bias circuit, respectively. In order to realize a low glitch energy, a cascode current switch has been employed. The simulation results of the designed DAC show a conversion rate of 65 MHz, a power dissipation of 71.7 mW, a DNL of /spl plusmn/0.2 LSB and an INL of /spl plusmn/0.8 LSB with a single power supply of 3.3 V for a 0.6 /spl mu/m n-well CMOS technology.