{"title":"2-D DOA estimating of multipath signals by exploitation of cyclostationarity","authors":"Liang Jin, M. Yao, Q. Yin","doi":"10.1109/MWSCAS.1998.759566","DOIUrl":"https://doi.org/10.1109/MWSCAS.1998.759566","url":null,"abstract":"In most wireless communication systems, two-dimensional directions of arrival (DOA) of multipath signals need to be found for spatial selective transmission. In this paper, we propose a new algorithm to estimate 2-D DOA of multiple narrow-band signals. A DOA cyclic matrix is constructed whose eigenvalues and eigenvectors can be simultaneously used to extract 2-D DOA without 2-D searches. By exploiting the temporal property of cyclostationarity, the signal detection capability is significantly improves. Besides, based on the decorrelation model for mobile terminal signals, the algorithm can be effectively extended to the coherent case without spatial smoothing and the loss of array aperture. Simulation results are given to illustrate the performance of the new algorithm.","PeriodicalId":338994,"journal":{"name":"1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116666761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Continuous time low-pass filter for video frequency applications","authors":"J. Sabadell, C. Aldea, S. Celma, P. Martínez","doi":"10.1109/MWSCAS.1998.759508","DOIUrl":"https://doi.org/10.1109/MWSCAS.1998.759508","url":null,"abstract":"In this paper a continuous-time 4/sup th/ order Butterworth lowpass filter based on current-mode processing is presented for applications over the video frequency range. Using a very low-cost 2.4 /spl mu/m CMOS process (Mietec), the circuit occupies 2.8 mm/sup 2/ and consumes 19 mW from a /spl plusmn/1.5 V supply. Experimental results are given for a 4.5 MHz to 12 MHz tunable lowpass filter with 58 dB of dynamic range at 10 MHz.","PeriodicalId":338994,"journal":{"name":"1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124873653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Turbulent effort imaging and analysis","authors":"Liaobo Peng, Xiaobo Peng","doi":"10.1109/MWSCAS.1998.759561","DOIUrl":"https://doi.org/10.1109/MWSCAS.1998.759561","url":null,"abstract":"When looking at objects in space, the turbulent effort of the Earth's atmosphere is an important factor. This paper focuses on the atmospheric effects on incoming light and image restoration methods to restore the formed nonisoplanatic image. Because of its turbulent nature, the atmosphere introduces the Kolmogorov phase onto the incoming light. In this paper, we use two layers of Kolmogorov phase to simulate the atmospheric turbulent effects, then form the nonisoplanatic image. We also analyze the Strehl ratio of the nonisoplanatic image. We show the compared results by use of two different restoration estimators.","PeriodicalId":338994,"journal":{"name":"1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122979917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Migrating group communication protocols to networks with mobile hosts","authors":"M. El-Gendy, H. Baraka, A. Fahmy","doi":"10.1109/MWSCAS.1998.759438","DOIUrl":"https://doi.org/10.1109/MWSCAS.1998.759438","url":null,"abstract":"There is a compelling need to include mobile hosts in many of today's computing applications especially in distributed applications. This paper introduces a new model, called Mobile Group Communication Model or MGCM, for implementing Process Groups and Group Communication as one tool for building reliable and fault-tolerant distributed applications on networks with mobile hosts. The model is based on a simple layered architecture that guarantees virtual synchrony and atomicity in addition to ordering requirements. A two-tier principle approach is used in designing the model that off-loads the work from mobile hosts to the set of mobile support stations. Simulation is conducted to test the model using the \"Ptolemy\" simulation tool.","PeriodicalId":338994,"journal":{"name":"1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122193736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 1.2 V micropower CMOS class-AB V-I converter for VLSI cells library design","authors":"Chi-Hung Lin, M. Ismail, T. Pimenta","doi":"10.1109/MWSCAS.1998.759507","DOIUrl":"https://doi.org/10.1109/MWSCAS.1998.759507","url":null,"abstract":"A micropower CMOS voltage-to-current converter is introduced which has a widely linear differential-input swing with a low signal-distortion with a minimum supply voltage of 1.2 V. This proposed circuit can achieve an almost rail-to-rail differential-input swing with at least 1.5 V supply-voltage. The proposed circuit uses class-AB linearisation to achieve widely linear input-swing in the saturation region. In a 1.2 /spl mu/m n-well CMOS process, the 3 dB frequency of the V-I converter is in a range of 44 M-57 MHz with different biases at the supply voltage of 1.5 V. High frequency capability (/spl ges/100 MHz) can be easily realized with higher supply voltages of 2 V, 3 V. The total power consumption is around 1.5 /spl mu/W at the minimum supply voltage of 1.2 V.","PeriodicalId":338994,"journal":{"name":"1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128795708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Performance of LRU block replacement algorithm with pre-fetching","authors":"R. Pendse, R. Bhagavathula","doi":"10.1109/MWSCAS.1998.759441","DOIUrl":"https://doi.org/10.1109/MWSCAS.1998.759441","url":null,"abstract":"An economical solution to the need for unlimited amounts of fast memory is a memory hierarchy, which takes advantage of locality and cost/performance of memory technologies. Most of the advanced block replacement algorithms exploit the presence of temporal locality in programs to achieve a better performing cache. A direct fallout of this approach is the increased overhead involved due to the complexity of the algorithm without any significant improvement in the cache performance. The performance of the cache could be improved if spatial locality present in the programs is further exploited. This paper presents the results of the investigation of the impact of pre-fetching techniques on the miss rates due to the basic Least Recently Used (LRU) block replacement algorithm. Simulations reveal an improvement of about 60% in the miss rates for instruction caches due to pre-fetching and a corresponding improvement of about 10% for data caches.","PeriodicalId":338994,"journal":{"name":"1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128576047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Performance of ATM switch using speedup networks","authors":"D. Abu-Saymeh, G. Chaudhry, A. Akram","doi":"10.1109/MWSCAS.1998.759538","DOIUrl":"https://doi.org/10.1109/MWSCAS.1998.759538","url":null,"abstract":"The biggest hurdle that faces the use of ATM for voice communication is cell delay and delay variance. This architecture utilizes the speedup concept where faster internal links and the availability of small internal queues reduce both blocking probability and cell delay. Adequate performance can be obtained using a speedup factor of 4 and internal queues of size 4. This work also presents the analytical and simulation models built to evaluate the performance. This work also studies the multicasting capability of this architecture. Finally, a high-level hardware implementation is described.","PeriodicalId":338994,"journal":{"name":"1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129004743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"AVLSI biologically-based motor control circuits","authors":"T. Zobel, B. Harris, S. DeWeerth","doi":"10.1109/MWSCAS.1998.759555","DOIUrl":"https://doi.org/10.1109/MWSCAS.1998.759555","url":null,"abstract":"We have developed motor control circuits based upon biological mechanisms of muscular control that demonstrate similar behaviour as motoneurons and muscle fibers. The circuits implement some key biologically-based motor control components including: (i) force-length and force-velocity characteristics associated with muscle actuation and (ii) stimulation rate characteristics associated with motoneurons. A small array of motoneuron and muscle fiber circuits that demonstrate an ordered recruitment scheme was implemented and tested for verification using analog VLSI circuits.","PeriodicalId":338994,"journal":{"name":"1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123982492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A frequency hopping synthesizer chip for GSM and DCS systems","authors":"J. Hakkinen, T. Rahkonen, J. Kostamovaara","doi":"10.1109/MWSCAS.1998.759505","DOIUrl":"https://doi.org/10.1109/MWSCAS.1998.759505","url":null,"abstract":"A versatile synthesizer chip capable of operating with an input signal of 2 GHz and a reference signal of 20 MHz was designed in AMS' 12 GHz 0.8 /spl mu/m BiCMOS process. The circuit includes the basic building blocks of a complete PLL-based synthesizer except for the VCO and the loop filter. Thus, the chip has an internal dual modulus prescaler operating in 8/9 or 16/17 mode, a VCO bit M counter, a VCO bit pulse swallow counter, a VCO bit reference counter, a phase-frequency detector and a lock-detector, all of which are programmed with external serial data. The level of the PFD output can be programmed digitally from 0.5 mA to 5.0 mA. Measurement results for a complete synthesizer board with reference signal frequency f/sub ref/=20 MHz, a loop filter and a hybrid VCO running at f/sub ref/=1.060 GHz, for example, are: the settling time of a 20 MHz frequency step /spl Delta/t=14 /spl mu/s, the output power P/sub out/=+9.7 dBm, the level of the 1/sup st/ reference spur is from -84 dBc to -64 dBc depending on the magnitude of the output current pulse of the PFD. The PLL chip consumes about 250 mA from a 5.0 V supply.","PeriodicalId":338994,"journal":{"name":"1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123638892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Nested loops optimization for multiprocessor architecture design","authors":"A. Leonardi, N. Passos, E.H.-M. Sha","doi":"10.1109/MWSCAS.1998.759519","DOIUrl":"https://doi.org/10.1109/MWSCAS.1998.759519","url":null,"abstract":"Multi-dimensional systems, including image processing, geophysical signal processing, and fluid dynamics, are becoming one of the most important targets of computational improvement studies. Most of the optimized solutions to those problems point to the use of application specific integrated circuits (ASICs). From the analysis of the multi-dimensional programming code, one can observe that nested loop like structures are often the most time consuming part. Designing ASICs with multiple processing units is usually the appropriate solution to achieve the required computational performance. In this paper, a new loop transformation algorithm, which allows an efficient utilization of the multiprocessor system is presented. Uniform nested loops are modeled as multi-dimensional data flow graphs. New loop structures are generated so that an arbitrary number of processors available in the system can run in parallel. An example demonstrates the effectiveness of the algorithm.","PeriodicalId":338994,"journal":{"name":"1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114349936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}