A frequency hopping synthesizer chip for GSM and DCS systems

A versatile synthesizer chip capable of operating with an input signal of 2 GHz and a reference signal of 20 MHz was designed in AMS' 12 GHz 0.8 /spl mu/m BiCMOS process. The circuit includes the basic building blocks of a complete PLL-based synthesizer except for the VCO and the loop filter. Thus, the chip has an internal dual modulus prescaler operating in 8/9 or 16/17 mode, a VCO bit M counter, a VCO bit pulse swallow counter, a VCO bit reference counter, a phase-frequency detector and a lock-detector, all of which are programmed with external serial data. The level of the PFD output can be programmed digitally from 0.5 mA to 5.0 mA. Measurement results for a complete synthesizer board with reference signal frequency f/sub ref/=20 MHz, a loop filter and a hybrid VCO running at f/sub ref/=1.060 GHz, for example, are: the settling time of a 20 MHz frequency step /spl Delta/t=14 /spl mu/s, the output power P/sub out/=+9.7 dBm, the level of the 1/sup st/ reference spur is from -84 dBc to -64 dBc depending on the magnitude of the output current pulse of the PFD. The PLL chip consumes about 250 mA from a 5.0 V supply.