Median biased Steiner tree heuristics in the rectilinear plane for low-power physical layout

Abstract

Two heuristics are proposed for the rectilinear Steiner-minimum tree (SMT) problem arising when interconnecting multiple terminals in a layout with obstacles. Efficient algorithms are implemented to convert circuit layouts into graphs. A set of reduction techniques are implemented to remove unfeasible vertices. These techniques delete an average of over 90% of the m Steiner candidates in O(m/sup 2/) time. The proposed SMT heuristics grow trees biased by the terminal distances of the n vertices in a graph in O(n/sup 2/.log n) time. The results obtained highlight their suitability to be used as wire length estimators in a power optimizing placement tool.