Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design最新文献_第2页

A compositional semantics of Simulink/Stateflow based on quantized state hybrid automata 一种基于量化状态混合自动机的Simulink/Stateflow组合语义

Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design Pub Date : 2019-10-09 DOI: 10.1145/3359986.3361198

J. Ro, Avinash Malik, P. Roop

{"title":"A compositional semantics of Simulink/Stateflow based on quantized state hybrid automata","authors":"J. Ro, Avinash Malik, P. Roop","doi":"10.1145/3359986.3361198","DOIUrl":"https://doi.org/10.1145/3359986.3361198","url":null,"abstract":"Simulink/Stateflow® is the de-facto tool for design of Cyber-physical Systems (CPS). CPS include hybrid systems, where a discrete controller guides a continuous plant. Hybrid systems are characterised by their continuous time dynamics with sudden discontinuities, caused by level/zero crossings. Stateflow can graphically capture hybrid phenomenon, making it popular with control engineers. However, Stateflow is unable to correctly and efficiently simulate complex hybrid systems, especially those characterised by even number of level crossings. In this paper we first propose a new formal model for hybrid systems called Quantized State Hybrid Input Output Automaton (QSHIOA). QSHIOA is used to give a deterministic semantics to Stateflow in addition to efficiently handling even number of level crossing detections. In the proposed compositional semantics, a network of Stateflow charts can be compiled into a network of QSHIOAs. Benchmark results show that in the median case, the proposed stateflow execution technique, via QSHIOA, is 84% faster than using the best variable-step size solvers in Simulink/Stateflow®.","PeriodicalId":331904,"journal":{"name":"Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123487843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Further sub-cycle and multi-cycle schedulling support for Bluespec Verilog 进一步支持Bluespec Verilog的子周期和多周期调度

Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design Pub Date : 2019-10-09 DOI: 10.1145/3359986.3361199

D. Greaves

{"title":"Further sub-cycle and multi-cycle schedulling support for Bluespec Verilog","authors":"D. Greaves","doi":"10.1145/3359986.3361199","DOIUrl":"https://doi.org/10.1145/3359986.3361199","url":null,"abstract":"Bluespec [13] is a hardware description language where all behaviour is expressed in rules that execute atomically. The standard compilation semantics for Bluespec enforce a particular mapping between rule firing and hardware clock cycles, such as a register only being updated by exactly one firing of at most one rule in any clock cycle. Also, the standard compiler does not introduce any additional state, such as credit-based or round-robin arbiters to guarantee fairness between rules over time. On the other hand, many useful hardware resources, such as complex ALUs and synchronous RAMs, are pipelined. Unlike typical high-level synthesis tools, in standard Bluespec such resources cannot be invoked using infix operators in expressions such as A[e] or e1*e2 since binding to specific instances and multi-clock cycle schedules are required. In this paper we extend the reference semantics of Bluespec to decouple it from clock cycles, allowing multiple updates to a register within one clock cycle and automatic instantiation of arbiters for multi-clock cycle behaviour. We describe the new semantic packing rules as extensions of our standard compilation rules and we report early results from an open-source, fully-functional implementation.","PeriodicalId":331904,"journal":{"name":"Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128541475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Compositional construction of bounded error over-approximations of acyclic interconnected continuous dynamical systems 无循环互联连续动力系统有界误差过逼近的组合构造

Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design Pub Date : 2019-10-09 DOI: 10.1145/3359986.3361210

Ratan Lal, P. Prabhakar

引用次数: 3

Encoding and monitoring responsibility sensitive safety rules for automated vehicles in signal temporal logic 基于信号时序逻辑的自动驾驶车辆责任敏感安全规则编码与监控

Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design Pub Date : 2019-10-09 DOI: 10.1145/3359986.3361203

Mohammad Hekmatnejad, Shakiba Yaghoubi, Adel Dokhanchi, H. B. Amor, Aviral Shrivastava, Lina Karam, Georgios Fainekos

{"title":"Encoding and monitoring responsibility sensitive safety rules for automated vehicles in signal temporal logic","authors":"Mohammad Hekmatnejad, Shakiba Yaghoubi, Adel Dokhanchi, H. B. Amor, Aviral Shrivastava, Lina Karam, Georgios Fainekos","doi":"10.1145/3359986.3361203","DOIUrl":"https://doi.org/10.1145/3359986.3361203","url":null,"abstract":"As Automated Vehicles (AV) get ready to hit the public roads unsupervised, many practical questions still remain open. For example, there is no commonly acceptable formal definition of what safe driving is. A formal definition of safe driving can be utilized in developing the vehicle behaviors as well as in certification and legal cases. Toward that goal, the Responsibility-Sensitive Safety (RSS) model was developed as a first step toward formalizing safe driving behavior upon which the broader AV community can expand. In this paper, we demonstrate that the RSS model can be encoded in Signal Temporal Logic (STL). Moreover, using the S-TaLiRo tools, we present a case study of monitoring RSS requirements on selected traffic scenarios from CommonRoad. We conclude that monitoring RSS rules encoded in STL is efficient even in heavy traffic scenarios. One interesting observation is that for the selected traffic data, vehicle parameters and response times, the RSS model violations are not frequent.","PeriodicalId":331904,"journal":{"name":"Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design","volume":"21 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132270754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 33

Securing implantable medical devices with runtime enforcement hardware 使用运行时强制硬件保护植入式医疗设备

Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design Pub Date : 2019-10-09 DOI: 10.1145/3359986.3361200

H. Pearce, Matthew M. Y. Kuo, P. Roop, Srinivas Pinisetty

{"title":"Securing implantable medical devices with runtime enforcement hardware","authors":"H. Pearce, Matthew M. Y. Kuo, P. Roop, Srinivas Pinisetty","doi":"10.1145/3359986.3361200","DOIUrl":"https://doi.org/10.1145/3359986.3361200","url":null,"abstract":"In recent years we have seen numerous proof-of-concept attacks on implantable medical devices such as pacemakers. Attackers aim to breach the strict operational constraints that these devices operate within, with the end-goal of compromising patient safety and health. Most efforts to prevent these kinds of attacks are informal, and focus on application- and system-level security --- for instance, using encrypted communications and digital certificates for program verification. However, these approaches will struggle to prevent all classes of attacks. Runtime verification has been proposed as a formal methodology for monitoring the status of implantable medical devices. Here, if an attack is detected a warning is generated. This leaves open the risk that the attack can succeed before intervention can occur. In this paper, we propose a runtime-enforcement based approach for ensuring patient security. Custom hardware is constructed for individual patients to ensure a safe minimum quality of service at all times. To ensure correctness we formally verify the hardware using a model-checker. We present our approach through a pacemaker case study and demonstrate that it incurs minimal overhead in terms of execution time and power consumption.","PeriodicalId":331904,"journal":{"name":"Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133365627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Establishing a refinement relation between binaries and abstract code 建立二进制代码和抽象代码之间的细化关系

Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design Pub Date : 2019-10-09 DOI: 10.1145/3359986.3361215

Freek Verbeek, Joshua A. Bockenek, Abhijith Bharadwaj, B. Ravindran, Ian Roessle

引用次数: 1

Modeling observability in adaptive systems to defend against advanced persistent threats 自适应系统的可观察性建模，以防御高级持续威胁

Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design Pub Date : 2019-10-09 DOI: 10.1145/3359986.3361208

Cody Kinneer, Ryan Wagner, Fei Fang, Claire Le Goues, D. Garlan

引用次数: 5

Approximate computing for multithreaded programs in shared memory architectures 共享内存体系结构中多线程程序的近似计算

Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design Pub Date : 2019-10-09 DOI: 10.1145/3359986.3361209

Bernard Nongpoh, Rajarshi Ray, A. Banerjee

{"title":"Approximate computing for multithreaded programs in shared memory architectures","authors":"Bernard Nongpoh, Rajarshi Ray, A. Banerjee","doi":"10.1145/3359986.3361209","DOIUrl":"https://doi.org/10.1145/3359986.3361209","url":null,"abstract":"In multicore and multicached architectures, cache coherence is ensured with a coherence protocol. However, the performance benefits of caching diminishes due to the cost associated with the protocol implementation. In this paper, we propose a novel technique to improve the performance of multithreaded programs running on shared-memory multicore processors by embracing approximate computing. Our idea is to relax the coherence requirement selectively in order to reduce the cost associated with a cache-coherence protocol, and at the same time, ensure a bounded QoS degradation with probabilistic reliability. In particular, we detect instructions in a multithreaded program that write to shared data, we call them Shared-Write-Access-Points (SWAPs), and propose an automated statistical analysis to identify those which can tolerate coherence faults. We call such SWAPs approximable. Our experiments on 9 applications from the SPLASH 3.0 benchmarks suite reveal that an average of 57% of the tested SWAPs are approximable. To leverage this observation, we propose an adapted cache-coherence protocol that relaxes the coherence requirement on stores from approximable SWAPs. Additionally, our protocol uses stale values for load misses due to coherence, the stale value being the version at the time of invalidation. We observe an average of 15% reduction in CPU cycles and 11% reduction in energy footprint from architectural simulation of the 9 applications using our approximate execution scheme.","PeriodicalId":331904,"journal":{"name":"Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131229171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1