Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design最新文献

A timeless model for the verification of quasi-periodic distributed systems 准周期分布式系统验证的永恒模型

Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design Pub Date : 2019-10-09 DOI: 10.1145/3359986.3361201

Maryam Dabaghchian, Zvonimir Rakamaric

{"title":"A timeless model for the verification of quasi-periodic distributed systems","authors":"Maryam Dabaghchian, Zvonimir Rakamaric","doi":"10.1145/3359986.3361201","DOIUrl":"https://doi.org/10.1145/3359986.3361201","url":null,"abstract":"A cyber-physical system often consists of distributed multi-rate periodic processes that communicate using message passing; each process owns a local clock not synchronized with others. We call such systems quasi-periodic distributed systems. Traditionally, one would model them using timed automata, thereby having to deal with high-complexity verification problems. Recently, several researchers proposed discrete-time abstractions based on the calendar model to make the verification more tractable. However, even the calendar model contains a notion of time in the form of a global clock. We propose a novel, timeless computation model for quasi-periodic distributed systems to facilitate their verification. The main idea behind our model is to judiciously replace synchronization using a global clock and calendar with synchronization over lengths of message buffers. We introduce a simple domain-specific language for programming of such systems and use it to formalize the semantics of both the calendar and timeless model. Then, we prove that our timeless model is an overapproximation of the calendar model. Finally, we evaluate our timeless model using several benchmarks.","PeriodicalId":331904,"journal":{"name":"Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126077548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design 第17届ACM-IEEE系统设计形式化方法与模型国际会议论文集

Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design Pub Date : 2019-10-09 DOI: 10.1145/3359986

J. Talpin, P. Derler, K. Schneider

引用次数: 0

Polyhedral fragments: an efficient representation for symbolically generating code for processor arrays 多面体片段:为处理器阵列象征性地生成代码的有效表示

Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design Pub Date : 2019-10-09 DOI: 10.1145/3359986.3361205

Michael Witterauf, Frank Hannig, J. Teich

{"title":"Polyhedral fragments: an efficient representation for symbolically generating code for processor arrays","authors":"Michael Witterauf, Frank Hannig, J. Teich","doi":"10.1145/3359986.3361205","DOIUrl":"https://doi.org/10.1145/3359986.3361205","url":null,"abstract":"To leverage the vast parallelism of loops, embedded loop accelerators often take the form of processor arrays with many, but simple processing elements. Each processing element executes a subset of a loop's iterations in parallel using instruction- and datalevel parallelism by tightly scheduling iterations using software pipelining and packing instructions into compact, individual programs. However, loop bounds are often unknown until runtime, which complicates the static generation of programs because they influence each program's control flow. Existing solutions, like generating and storing all possible programs or full just-in-time compilation, are prohibitively expensive, especially in embedded systems. As a remedy, we propose a hybrid approach introducing a tree-like program representation, whose generation front-loads all intractable sub-problems to compile time, and from which all concrete program variants can efficiently be stitched together at runtime. The tree consists of so-called polyhedral fragments that represent concrete program parts and are annotated with iteration-dependent conditions. We show that both this representation is both space- and time-efficient: it requires polynomial space to store---whereas storing all possibly generated programs is non-polynomial---and polynomial time to evaluate---whereas just-in-time compilation requires solving NP-hard problems. In a case study, we show for a representative loop program that using a tree of polyhedral fragments saves 98.88 % of space compared to storing all program variants.","PeriodicalId":331904,"journal":{"name":"Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130019385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A compositional approach for real-time machine learning 实时机器学习的组合方法

Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design Pub Date : 2019-10-09 DOI: 10.1145/3359986.3361204

Nathan Allen, Yash Raje, J. Ro, P. Roop

{"title":"A compositional approach for real-time machine learning","authors":"Nathan Allen, Yash Raje, J. Ro, P. Roop","doi":"10.1145/3359986.3361204","DOIUrl":"https://doi.org/10.1145/3359986.3361204","url":null,"abstract":"Cyber-Physical Systems are highly safety critical, especially since they have to provide both functional and timing guarantees. Increasingly, Cyber-Physical Systems such as autonomous vehicles are relying on Artificial Neural Networks in their decision making and this has obvious safety implications. While many formal approaches have been recently developed for ensuring functional correctness of machine learning modules involving Artificial Neural Networks, the issue of timing correctness has received scant attention. This paper proposes a new compiler from the well known Keras Neural Network library to hardware to mitigate the above problem. In the developed approach, we compile networks of Artificial Neural Networks, called Meta Neural Networks, to hardware implementations using a new synchronous semantics for their execution. The developed semantics enables compilation of Meta Neural Networks to a parallel hardware implementation involving limited hardware resources. The developed compiler is semantics driven and guarantees that the generated implementation is deterministic and time predictable. The compiler also provides a better alternative for the realisation of non-linear functions in hardware. Overall, we show that the developed approach is significantly more efficient than a software approach, without the burden of complex algorithms needed for software Worst Case Execution Time analysis.","PeriodicalId":331904,"journal":{"name":"Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design","volume":"598 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121979575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Security analysis of cloud-connected industrial control systems using combinatorial testing 基于组合测试的云连接工业控制系统安全性分析

Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design Pub Date : 2019-10-09 DOI: 10.1145/3359986.3361211

P. Tran-Jørgensen, T. Kulik, Jalil Boudjadar, P. Larsen

引用次数: 2

Detecting security leaks in hybrid systems with information flow analysis 基于信息流分析的混合系统安全漏洞检测

Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design Pub Date : 2019-10-09 DOI: 10.1145/3359986.3361212

L. V. Nguyen, G. Mohan, James Weimer, O. Sokolsky, Insup Lee, R. Alur

{"title":"Detecting security leaks in hybrid systems with information flow analysis","authors":"L. V. Nguyen, G. Mohan, James Weimer, O. Sokolsky, Insup Lee, R. Alur","doi":"10.1145/3359986.3361212","DOIUrl":"https://doi.org/10.1145/3359986.3361212","url":null,"abstract":"Information flow analysis is an effective way to check useful security properties, such as whether secret information can leak to adversaries. Despite being widely investigated in the realm of programming languages, information-flow-based security analysis has not been widely studied in the domain of cyber-physical systems (CPS). CPS provide interesting challenges to traditional type-based techniques, as they model mixed discrete-continuous behaviors and are usually expressed as a composition of state machines. In this paper, we propose a lightweight static analysis methodology that enables information security properties for CPS models. We introduce a set of security rules for hybrid automata that characterizes the property of non-interference. Based on those rules, we propose an algorithm that generates security constraints between each sub-component of hybrid automata, and then transforms these constraints into a directed dependency graph to search for non-interference violations. The proposed algorithm can be applied directly to parallel compositions of automata without resorting to model-flattening techniques. Our static checker works on hybrid systems modeled in Simulink/Stateflow format and decides whether or not the model satisfies non-interference given a user-provided security annotation for each variable. Moreover, our approach can also infer the security labels of variables, allowing a designer to verify the correctness of partial security annotations. We demonstrate the potential benefits of the proposed methodology on two case studies.","PeriodicalId":331904,"journal":{"name":"Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127501301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Security-driven metrics and models for efficient evaluation of logic encryption schemes 用于逻辑加密方案有效评估的安全驱动度量和模型

Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design Pub Date : 2019-10-09 DOI: 10.1145/3359986.3361207

Yinghua Hu, Vivek V. Menon, A. Schmidt, Joshua S. Monson, M. French, P. Nuzzo

引用次数: 9

RTL bug localization through LTL specification mining (WIP) 通过LTL规范挖掘(WIP)进行RTL错误定位

Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design Pub Date : 2019-10-09 DOI: 10.1145/3359986.3361202

Vighnesh Iyer, Donggyu Kim, B. Nikolić, S. Seshia

{"title":"RTL bug localization through LTL specification mining (WIP)","authors":"Vighnesh Iyer, Donggyu Kim, B. Nikolić, S. Seshia","doi":"10.1145/3359986.3361202","DOIUrl":"https://doi.org/10.1145/3359986.3361202","url":null,"abstract":"As the complexity of contemporary hardware designs continues to grow, functional verification demands more effort and resources in the design cycle than ever. As a result, manually debugging RTL designs is extremely challenging even with full signal traces after detecting errors in chip-level software simulation or FPGA emulation. Therefore, it is necessary to reduce the burden of verification by automating RTL debugging processes. In this paper, we propose a novel approach for debugging with the use of LTL specification mining. In this approach, we extract fine-grained assertions that are implicitly encoded in the RTL design, representing the designer's assumptions, to localize bugs that are only detected when high-level properties are violated from long-running full-system simulations. We employ template-based RTL spec mining to infer both safety and bounded liveness properties. We propose strategies to convert multi-bit signals to atomic propositions based on common RTL design idioms such as ready-valid handshakes and specific state transitions using automatic static analysis. Our initial results with a tiny RISC-V core design show that this methodology is promising for localizing bugs in time and space by demonstrating that the mined fine-grained LTL properties are violated before a high-level test failure condition occurs, such as a timeout or hanging, and can point to specific lines of suspect RTL.","PeriodicalId":331904,"journal":{"name":"Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114518123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Logical specification and uniform synthesis of robust controllers 鲁棒控制器的逻辑规范与统一综合

Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design Pub Date : 2019-10-09 DOI: 10.1145/3359986.3361213

P. Pandya, A. Wakankar

{"title":"Logical specification and uniform synthesis of robust controllers","authors":"P. Pandya, A. Wakankar","doi":"10.1145/3359986.3361213","DOIUrl":"https://doi.org/10.1145/3359986.3361213","url":null,"abstract":"This paper investigates the synthesis of robust controllers from a logical specification of regular properties given in an interval temporal logic QDDC. Our specification encompasses both hard robustness and soft robustness. Here, hard robustness guarantees the invariance of commitment under relaxed (weakened) assumptions. A systematic framework for logically specifying the assumption weakening by means of a QDDC formula Rb(A), called Robustness criterion, is presented. This can be used with any user specified assumption DA to obtain a relaxed (weakened) assumption Rb(DA). A variety of robustness criteria encompassing some existing notions such as k, b resilience as well as some new notions like tolerating non-burst errors and recovery from transient errors are formulated logically. The soft robustness pertains to the ability of the controller to maintain the commitment for as many inputs as possible, irrespective of any assumption. We present a uniform method for the synthesis of a robust controller which guarantees the invariance of specified hard robustness and it optimizes the expected value of occurrence of commitment across input sequences. Through the case study of a synchronous bus arbiter, we experimentally show the impact of variety of hard robustness criteria as well as the soft robustness on the ability of the synthesized controllers to meet the commitment \"as much as possible\".","PeriodicalId":331904,"journal":{"name":"Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115724617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Lattice-based SMT for program verification 用于程序验证的基于格子的SMT

Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design Pub Date : 2019-10-09 DOI: 10.1145/3359986.3361214

Karine Even-Mendoza, A. Hyvärinen, Hana Chockler, N. Sharygina

{"title":"Lattice-based SMT for program verification","authors":"Karine Even-Mendoza, A. Hyvärinen, Hana Chockler, N. Sharygina","doi":"10.1145/3359986.3361214","DOIUrl":"https://doi.org/10.1145/3359986.3361214","url":null,"abstract":"We present a lattice-based satisfiability modulo theory for verification of programs with library functions, for which the mathematical libraries supporting these functions contain a high number of equations and inequalities. Common strategies for dealing with library functions include treating them as uninterpreted functions or using the theories under which the functions are fully defined. The full definition could in most cases lead to instances that are too large to solve efficiently. Our lightweight theory uses lattices for efficient representation of library functions by a subset of guarded literals. These lattices are constructed from equations and inequalities of properties of the library functions. These subsets are found during the lattice traversal. We generalise the method to a number of lattices for functions whose values depend on each other in the program, and we describe a simultaneous traversal algorithm of several lattices, so that a combination of guarded literals from all lattices does not lead to contradictory values of their variables. We evaluate our approach on benchmarks taken from the robotics community, and our experimental results demonstrate that we are able to solve a number of instances that were previously unsolvable by existing SMT solvers.","PeriodicalId":331904,"journal":{"name":"Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121381985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1