发布求助
文献互助 智能选刊 最新文献

2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)最新文献

筛选
英文 中文
Work-in-Progress: DRAM-MaUT: DRAM Address Mapping Unveiling Tool for ARM Devices 正在进行的工作:DRAM- maut: ARM设备的DRAM地址映射揭示工具
2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) Pub Date : 2022-10-01 DOI: 10.1109/CASES55004.2022.00027
Anandpreet Kaur, Pravin Srivastav, Bibhas Ghoshal
{"title":"Work-in-Progress: DRAM-MaUT: DRAM Address Mapping Unveiling Tool for ARM Devices","authors":"Anandpreet Kaur, Pravin Srivastav, Bibhas Ghoshal","doi":"10.1109/CASES55004.2022.00027","DOIUrl":"https://doi.org/10.1109/CASES55004.2022.00027","url":null,"abstract":"In this paper, we propose a software based technique to reveal the DRAM geometry information which is essential in studying various memory based attacks mounted on embedded devices such as Row Hammer. We apply a reverse-engineering approach for retrieving row, column, bank bits of DRAM which may significantly increase the number of bit flips in a Row Hammer test. To the best of our knowledge, the proposed technique is the first work to disclose the entire information about the DRAM chips of any embedded architecture.","PeriodicalId":331181,"journal":{"name":"2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)","volume":"375 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122774449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Work-in-Progress: Smart data reduction in SLAM methods for embedded systems 正在进行的工作:嵌入式系统SLAM方法中的智能数据缩减
2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) Pub Date : 2022-10-01 DOI: 10.1109/CASES55004.2022.00018
Quentin Picard, S. Chevobbe, Mehdi Darouich, Zoe Mandelli, Mathieu Carrier, Jean-Yves Didier
{"title":"Work-in-Progress: Smart data reduction in SLAM methods for embedded systems","authors":"Quentin Picard, S. Chevobbe, Mehdi Darouich, Zoe Mandelli, Mathieu Carrier, Jean-Yves Didier","doi":"10.1109/CASES55004.2022.00018","DOIUrl":"https://doi.org/10.1109/CASES55004.2022.00018","url":null,"abstract":"Visual-inertial simultaneous localization and mapping methods (SLAM) process and store large amounts of data based on image sequences to estimate accurate and robust real-time trajectories. Real-time performances, memory management and low power consumption are critical for embedded SLAM with restrictive hardware resources. We aim at reducing the amount of injected input data in SLAM algorithms and, thereby, the memory footprint while providing improved real-time performances. Two decimation approaches are used, constant filtering and adaptive filtering. The first one decimates input images to reduce frame rate (from 20 to 10, 7, 5 and 2 fps). The latter one uses inertial measurements to reduce the frame rate when no significant motion is detected. Applied to SLAM methods, it produces more accurate trajectories than the constant filtering approach, while further reducing the amount of injected data up to 85%. It also impacts the resource utilization by reducing up to an average of 91% the peak of memory consumption.","PeriodicalId":331181,"journal":{"name":"2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116754865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Work in Progress: ACAC: An Adaptive Congestion-aware Approximate Communication Mechanism for Network-on-Chip Systems 在进行中的工作:ACAC:一种适应拥塞感知的片上网络近似通信机制
2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) Pub Date : 2022-10-01 DOI: 10.1109/CASES55004.2022.00009
Shize Zhou, Yongqi Xue, Siyue Li, Jinlun Ji, Tong Cheng, Li Li, Yuxiang Fu
{"title":"Work in Progress: ACAC: An Adaptive Congestion-aware Approximate Communication Mechanism for Network-on-Chip Systems","authors":"Shize Zhou, Yongqi Xue, Siyue Li, Jinlun Ji, Tong Cheng, Li Li, Yuxiang Fu","doi":"10.1109/CASES55004.2022.00009","DOIUrl":"https://doi.org/10.1109/CASES55004.2022.00009","url":null,"abstract":"Data-intensive applications, such as machine learning and pattern recognition, result in heavy Network-on-Chip (NoC) communication loads and a tremendous increase in the communication latency. At the same time, the error-tolerant nature of these applications makes approximate communication an effective way to relieve the sharp increase of the network latency. This paper proposes an adaptive congestion-aware approximate communication mechanism (ACAC) that can alleviate the communication congestion of NoC systems in heavy communication loads. Our cycle-accurate simulations have shown that the proposed ACAC effectively reduces the network latency similar to ABDTR under a 22% to 52% lower data approximate ratio and significantly decreases the additional compression control traffic volume under real applications.","PeriodicalId":331181,"journal":{"name":"2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127574491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Work-in-Progress: Efficient Low-latency Near-Memory Addition 正在进行的工作:高效低延迟近内存添加
2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) Pub Date : 2022-10-01 DOI: 10.1109/CASES55004.2022.00023
Alexander Reaugh, S. A. Salehi
{"title":"Work-in-Progress: Efficient Low-latency Near-Memory Addition","authors":"Alexander Reaugh, S. A. Salehi","doi":"10.1109/CASES55004.2022.00023","DOIUrl":"https://doi.org/10.1109/CASES55004.2022.00023","url":null,"abstract":"Near-memory computing provides energy and time saving for performing bitwise-parallel operations in computing systems. Bitwise parallelism of addition, however, is restricted due to carry propagation. In this work, we propose new circuits for performing digit-wise near-memory addition for ternary data. The proposed architecture can perform carry-free addition and, despite the number of digits of the input operands, its latency is 21 memory cycles which is the lowest latency compared to prior work.","PeriodicalId":331181,"journal":{"name":"2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126968886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Work-in-Progress: Prediction-based Fine-Grained LDPC Reading to Enhance High-Density Flash Read Performance 正在进行的工作:基于预测的细粒度LDPC读取以提高高密度闪存读取性能
2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) Pub Date : 2022-10-01 DOI: 10.1109/CASES55004.2022.00013
Yajuan Du, Yuan Gao, Qiao Li
{"title":"Work-in-Progress: Prediction-based Fine-Grained LDPC Reading to Enhance High-Density Flash Read Performance","authors":"Yajuan Du, Yuan Gao, Qiao Li","doi":"10.1109/CASES55004.2022.00013","DOIUrl":"https://doi.org/10.1109/CASES55004.2022.00013","url":null,"abstract":"LDPC codes have been widely applied in high-density flash memories, e.g., TLC flash and QLC flash, to ensure data reliability. In order to reduce the read latency of high-density flash memories, this paper proposes a prediction-based fine-grained LDPC reading method, named as PreLDPC. From a preliminary study, we observe that the ratio of cells that lie in error-prone areas (i.e., the areas between two adjacent cell states) is closely related to the final read level for successful decoding. Based on this observation, PreLDPC predicts the read level for LDPC reading, which could avoid excessive unnecessary read-retries. Furthermore, a fine-grained read method with fine sub-levels is used in the read-retry iteration for read latency reduction. From experimental results over real-world workloads on Disksim with SSD extensions, the effectiveness of PreLDPC on reducing read latency is verified in high-density flash memories.","PeriodicalId":331181,"journal":{"name":"2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133832018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Work-in-Progress: Object Detection Acceleration Method by Improving Execution Efficiency of AI Device 正在进行的:提高AI设备执行效率的目标检测加速方法
2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) Pub Date : 2022-10-01 DOI: 10.1109/CASES55004.2022.00014
Yoshikazu Watanabe, Yuki Kobayashi, N. Nakajima, Takashi Takenaka, Hiroyoshi Miyano
{"title":"Work-in-Progress: Object Detection Acceleration Method by Improving Execution Efficiency of AI Device","authors":"Yoshikazu Watanabe, Yuki Kobayashi, N. Nakajima, Takashi Takenaka, Hiroyoshi Miyano","doi":"10.1109/CASES55004.2022.00014","DOIUrl":"https://doi.org/10.1109/CASES55004.2022.00014","url":null,"abstract":"In recent years, there has been a growing need to perform object detection at the edge. Since the edge environment has tight physical constraints, the efficient use of AI devices is a key challenge to execute object detection at high throughput. In this paper, we propose an object detection acceleration method which uses two types of one-stage detectors in combination. After detecting object candidates by a lightweight detector, the method generates aggregated images by combining the candidate images and executes the second more accurate detector on the aggregated images to improve execution efficiency of AI devices. Our evaluations confirmed that the proposed method can speed up object detection by up to eight times for a license plate detection task with almost no accuracy degradation. We conducted evaluations with a car detection task and a pose estimation task as well and confirmed the broad applicability of the proposed method.","PeriodicalId":331181,"journal":{"name":"2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123528138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Work-in-Progress: Reliability Evaluation of Power SCADA System with Three-Layer IDS 基于三层IDS的电力SCADA系统可靠性评估
2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) Pub Date : 2022-10-01 DOI: 10.1109/CASES55004.2022.00007
Yenan Chen, Linsen Li, Zhaoqian Zhu, Yue Wu
{"title":"Work-in-Progress: Reliability Evaluation of Power SCADA System with Three-Layer IDS","authors":"Yenan Chen, Linsen Li, Zhaoqian Zhu, Yue Wu","doi":"10.1109/CASES55004.2022.00007","DOIUrl":"https://doi.org/10.1109/CASES55004.2022.00007","url":null,"abstract":"The SCADA (Supervisory Control And Data Acquisition) has become ubiquitous in industrial control systems. However, it may be exposed to cyber attack threats when it accesses the Internet. We propose a three-layer IDS (Intrusion Detection System) model, which integrates three main functions: access control, flow detection and password authentication. We use the reliability test system IEEE RTS-79 to evaluate the reliability. The experimental results provide insights into the establishment of the power SCADA system reliability enhancement strategies.","PeriodicalId":331181,"journal":{"name":"2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117231324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Work-in-Progress: A Processing-in-Pixel Accelerator based on Multi-level HfOx ReRAM 正在进行的工作:基于多层次HfOx ReRAM的像素级处理加速器
2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) Pub Date : 2022-10-01 DOI: 10.1109/CASES55004.2022.00025
Minhaz Abedin, A. Roohi, N. Cady, Shaahin Angizi
{"title":"Work-in-Progress: A Processing-in-Pixel Accelerator based on Multi-level HfOx ReRAM","authors":"Minhaz Abedin, A. Roohi, N. Cady, Shaahin Angizi","doi":"10.1109/CASES55004.2022.00025","DOIUrl":"https://doi.org/10.1109/CASES55004.2022.00025","url":null,"abstract":"This work paves the way to realize a processing-in-pixel accelerator based on a multi-level HfOx ReRAM as a flexible, energy-efficient, and high-performance solution for real-time and smart image processing at edge devices. The proposed design intrinsically implements and supports a coarse-grained convolution operation in low-bit-width neural networks leveraging a novel compute-pixel with non-volatile weight storage at the sensor side. Our evaluations show that such a design can remarkably reduce the power consumption of data conversion and transmission to an off-chip processor maintaining accuracy compared with the recent in-sensor computing designs.","PeriodicalId":331181,"journal":{"name":"2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127768162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
CASES 2022 Program Committee 2022项目委员会
2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) Pub Date : 2022-10-01 DOI: 10.1109/cases55004.2022.00006
{"title":"CASES 2022 Program Committee","authors":"","doi":"10.1109/cases55004.2022.00006","DOIUrl":"https://doi.org/10.1109/cases55004.2022.00006","url":null,"abstract":"","PeriodicalId":331181,"journal":{"name":"2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114763555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Work in Progress: Emulation of biological tissues on an FPGA 正在进行的工作:在FPGA上模拟生物组织
2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) Pub Date : 2022-10-01 DOI: 10.1109/cases55004.2022.00026
Jerry Jacob, Sucheta Sehgal, Nitish D. Patel
{"title":"Work in Progress: Emulation of biological tissues on an FPGA","authors":"Jerry Jacob, Sucheta Sehgal, Nitish D. Patel","doi":"10.1109/cases55004.2022.00026","DOIUrl":"https://doi.org/10.1109/cases55004.2022.00026","url":null,"abstract":"Models have been formulated to emulate various biological cells’ action potentials (AP). Most of these are computationally expensive and unsuitable for FPGA implementations. The Resonant Model (RM) is an alternative that offers good accuracy with real-time FPGA implementation. This WIP charts the RM validation path for tissue level emulation.","PeriodicalId":331181,"journal":{"name":"2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133764737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信