Work-in-Progress: Efficient Low-latency Near-Memory Addition

Abstract

Near-memory computing provides energy and time saving for performing bitwise-parallel operations in computing systems. Bitwise parallelism of addition, however, is restricted due to carry propagation. In this work, we propose new circuits for performing digit-wise near-memory addition for ternary data. The proposed architecture can perform carry-free addition and, despite the number of digits of the input operands, its latency is 21 memory cycles which is the lowest latency compared to prior work.