10th IEEE International Symposium on Industrial Embedded Systems (SIES)最新文献

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Protecting FPGA-based automotive systems against soft errors through reduced precision redundancy 通过降低精度冗余,保护基于fpga的汽车系统免受软错误的影响
10th IEEE International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2015-06-08 DOI: 10.1109/SIES.2015.7185057
W. Stechele
{"title":"Protecting FPGA-based automotive systems against soft errors through reduced precision redundancy","authors":"W. Stechele","doi":"10.1109/SIES.2015.7185057","DOIUrl":"https://doi.org/10.1109/SIES.2015.7185057","url":null,"abstract":"Due to their beneficial performance/power/cost ratio, hybrid systems of CPU and FPGA devices are gaining interest from automotive domain. However, FPGA devices suffer from their soft error susceptibility in safety-critical applications. Traditional protection mechanisms like Triple Module Redundancy are well known from space applications, but seem too costly for automotive. In this paper, we introduce first ideas on extending the well-known reduced precision redundancy methods from Shanbhag towards protecting FPGA devices against soft errors by adding CPU-based redundancy. The cost of protection is estimated for a fuel injection control unit with respect to chip area and CPU time overhead, as compared to conventional TMR-based protection.","PeriodicalId":328716,"journal":{"name":"10th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"9 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130146842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
SMT-based synthesis of TTEthernet schedules: A performance study 基于smt的以太网调度综合:性能研究
10th IEEE International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2015-06-08 DOI: 10.1109/SIES.2015.7185055
Francisco Pozo, G. Rodríguez-Navas, H. Hansson, W. Steiner
{"title":"SMT-based synthesis of TTEthernet schedules: A performance study","authors":"Francisco Pozo, G. Rodríguez-Navas, H. Hansson, W. Steiner","doi":"10.1109/SIES.2015.7185055","DOIUrl":"https://doi.org/10.1109/SIES.2015.7185055","url":null,"abstract":"Time-triggered networks, like TTEthernet, require adoption of a predefined schedule to guarantee low communication latency and minimal jitter. The synthesis of such schedules is a problem known to be NP-complete. In the past, specialized solvers have been used for synthesizing time-triggered schedules, but more recently general-purpose tools like Satisfiability Modulo Theories (SMT) solvers have reported synthesis of large network schedules in reasonable time for industrial purposes. An interesting characteristic of any general-purpose tool is that its configuration parameters can be tuned in order to fit specific problems and achieve increased performance. This paper presents a study identifying and assessing which SMT solver parameters have the highest impact on the performance when synthesizing schedules for time-triggered networks. The results show that with appropriate values of certain parameters, the time can be reduced significantly, up to 75% in the best cases compared to previous work.","PeriodicalId":328716,"journal":{"name":"10th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117089170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Using BIP to reinforce correctness of resource-constrained IoT applications 使用BIP来加强资源受限物联网应用的正确性
10th IEEE International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2015-06-08 DOI: 10.1109/SIES.2015.7185066
A. Lekidis, Emmanouela Stachtiari, P. Katsaros, M. Bozga, C. Georgiadis
{"title":"Using BIP to reinforce correctness of resource-constrained IoT applications","authors":"A. Lekidis, Emmanouela Stachtiari, P. Katsaros, M. Bozga, C. Georgiadis","doi":"10.1109/SIES.2015.7185066","DOIUrl":"https://doi.org/10.1109/SIES.2015.7185066","url":null,"abstract":"Internet of Things (IoT) systems process and respond to multiple (external) events, while performing computations for a Sense-Compute-Control (SCC) or a Sense-Only (SO) goal. Given the limitations of the interconnected resource-constrained devices, the execution environment can be based on an appropriate operating system for the IoT. The development effort can be reduced, when applications are built on top of RESTful web services, which can be shared and reused. However, the asynchronous communication between remote nodes is prone to event scheduling delays, which cannot be predicted and taken into account while programming the application. Long delays in message processing and communication, due to packet collisions, are avoided by carefully choosing the data transmission frequencies between the system's nodes. But even when specialized simulators are available, it is still a hard challenge to guarantee the functional and non-functional requirements at the application and system levels. In this article, we introduce a model-based rigorous analysis approach using the BIP component framework. We present a BIP model for IoT applications running on the Contiki OS. At the application level, we verify qualitative properties for service responsiveness requirements, whereas at the system level we can validate qualitative and quantitative properties using statistical model checking. We present results for an application scenario running on a distributed system infrastructure.","PeriodicalId":328716,"journal":{"name":"10th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"463 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125819698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Virtual prototyping of heterogeneous dynamic platforms using Open Virtual Platforms 基于开放虚拟平台的异构动态平台虚拟样机
10th IEEE International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2015-06-08 DOI: 10.1109/SIES.2015.7185053
Leonard Masing, Stephan Werner, J. Becker
{"title":"Virtual prototyping of heterogeneous dynamic platforms using Open Virtual Platforms","authors":"Leonard Masing, Stephan Werner, J. Becker","doi":"10.1109/SIES.2015.7185053","DOIUrl":"https://doi.org/10.1109/SIES.2015.7185053","url":null,"abstract":"Heterogeneous dynamic computing platforms are one of the big trends in today's electronic world. These platforms typically feature different General-Purpose-Processors (GPP) combined with accelerators on a reconfigurable layer. However, this necessitates specialized programming models and an Operating System (OS) for dealing with the dynamicity. To allow the early development of the system software, the tool-chain and to help in the design space exploration, high-level simulations offer a possible solution. In this paper we evaluate the application of Open Virtual Platforms (OVP) for the modelling of a heterogeneous dynamic platform. The OVP high-level simulations are extended by introducing peripherals to model the abilities of such a platform. Specifically, a generic I/O device, a communication device for a distributed platform and an accelerator interface with a reconfigurable accelerator model is implemented and integrated into a simulated platform. Different approaches are presented and the insights and results gained during the development process are discussed regarding speed and applicability to the use case.","PeriodicalId":328716,"journal":{"name":"10th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134312863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Energy- and latency-aware simulation of battery-operated wireless embedded networks for home automation 用于家庭自动化的电池供电无线嵌入式网络的能量和延迟感知仿真
10th IEEE International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2015-06-08 DOI: 10.1109/SIES.2015.7185050
D. Pfefferkorn, H. Jeschke, H. Blume
{"title":"Energy- and latency-aware simulation of battery-operated wireless embedded networks for home automation","authors":"D. Pfefferkorn, H. Jeschke, H. Blume","doi":"10.1109/SIES.2015.7185050","DOIUrl":"https://doi.org/10.1109/SIES.2015.7185050","url":null,"abstract":"In this paper we present a simulation-based approach to determine the impact of placement and duty-cycle of wireless embedded sensor actor network (WESAN) nodes on various parameters, such as expectable lifetime, latency and overall operability. It accurately reflects hardware characteristics, e.g. power consumption, switching times, and therefore enables analysis of the platform-specific effects on the nodes' and the network's performance. In order to validate the approach, a case study involving a battery-operated door access control application is presented.","PeriodicalId":328716,"journal":{"name":"10th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131950034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fail-operational in safety-related automotive multi-core systems 与安全相关的汽车多核系统的故障操作
10th IEEE International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2015-06-08 DOI: 10.1109/SIES.2015.7185051
André Kohn, Michael Kasmeyer, Rolf Schneider, A. Roger, C. Stellwag, A. Herkersdorf
{"title":"Fail-operational in safety-related automotive multi-core systems","authors":"André Kohn, Michael Kasmeyer, Rolf Schneider, A. Roger, C. Stellwag, A. Herkersdorf","doi":"10.1109/SIES.2015.7185051","DOIUrl":"https://doi.org/10.1109/SIES.2015.7185051","url":null,"abstract":"Dynamically expendable real-time systems are an essential improvement over current future automotive E/E architectures. New functions and applications like automated driving or the subsequent activation of features require a different approach. This also applies to existing architectures which lack enhanced safety concepts beyond common fail-safe systems. Especially, electronic components without mechanical fallback require a fail-operational implementation to guarantee a correct safety-behavior. Although common hardware architectures already provide a couple of safety features, hardware-supported features to realize such systems are under research. In our work-in-progress paper we provide an overview on existing approaches and present future concepts for the implementation of fail-operational systems on a multi-core processor.","PeriodicalId":328716,"journal":{"name":"10th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131111207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Periodic thermal management for hard real-time systems 硬实时系统的周期性热管理
10th IEEE International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2015-06-08 DOI: 10.1109/SIES.2015.7185040
Long Cheng, Kai Huang, Gang Chen, Biao Hu, A. Knoll
{"title":"Periodic thermal management for hard real-time systems","authors":"Long Cheng, Kai Huang, Gang Chen, Biao Hu, A. Knoll","doi":"10.1109/SIES.2015.7185040","DOIUrl":"https://doi.org/10.1109/SIES.2015.7185040","url":null,"abstract":"Due to growing power density, on-chip temperature increases rapidly, which has hampered the reliability and performance of modern real-time systems. This paper studies how to minimize the peak temperature for hard real-time systems under hard real-time constraints with periodic thermal management. A closed-form representation of the peak temperature for such a periodic scheme is derived to tackle this problem. Based on this closed-form and the arrival curve model which is used to model the system workload, two approaches that can derive periodic thermal management are proposed to minimize the peak temperature for a given event stream with a trade-off between complexity and accuracy. Case studies show that our approaches can achieve similar or better level of peak temperature but with two or three orders of magnitude lower computation expense compared to previous work.","PeriodicalId":328716,"journal":{"name":"10th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129189812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Resource sharing under global scheduling with partial processor bandwidth 局部处理器带宽全局调度下的资源共享
10th IEEE International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2015-06-08 DOI: 10.1109/SIES.2015.7185061
Sara Afshar, M. Behnam, R. J. Bril, Thomas Nolte
{"title":"Resource sharing under global scheduling with partial processor bandwidth","authors":"Sara Afshar, M. Behnam, R. J. Bril, Thomas Nolte","doi":"10.1109/SIES.2015.7185061","DOIUrl":"https://doi.org/10.1109/SIES.2015.7185061","url":null,"abstract":"Resource efficient approaches are of great importance for resource constrained embedded systems. In this paper, we present an approach targeting systems where tasks of a critical application are partitioned on a multi-core platform and by using resource reservation techniques, the remaining bandwidth capacity on each core is utilized for one or a set of non-critical application(s). To provide a resource efficient solution and to exploit the potential parallelism of the extra applications on the multi-core processor, global scheduling is used to schedule the tasks of the non-critical applications. Recently a specific instantiation of such a system has been studied where tasks do not share resources other than the processor. In this paper, we enable semaphore-based resource sharing among tasks within critical and non-critical applications using a suspension-based synchronization protocol. Tasks of non-critical applications have partial access to the processor bandwidth. The paper provides the systems schedulability analysis where blocking due to resource sharing is bounded. Further, we perform experimental evaluations under balanced and unbalanced allocation of tasks of a critical application to cores.","PeriodicalId":328716,"journal":{"name":"10th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127872720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
WCET analysis methods: Pitfalls and challenges on their trustworthiness WCET分析方法:可信度的陷阱与挑战
10th IEEE International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2015-06-08 DOI: 10.1109/SIES.2015.7185039
J. Abella, Carles Hernández, E. Quiñones, F. Cazorla, P. Conmy, M. Azkarate-askasua, Jon Pérez, E. Mezzetti, T. Vardanega
{"title":"WCET analysis methods: Pitfalls and challenges on their trustworthiness","authors":"J. Abella, Carles Hernández, E. Quiñones, F. Cazorla, P. Conmy, M. Azkarate-askasua, Jon Pérez, E. Mezzetti, T. Vardanega","doi":"10.1109/SIES.2015.7185039","DOIUrl":"https://doi.org/10.1109/SIES.2015.7185039","url":null,"abstract":"In the last three decades a number of methods have been devised to find upper-bounds for the execution time of critical tasks in time-critical systems. Most of such methods aim to compute Worst-Case Execution Time (WCET) estimates, which can be used as trustworthy upper-bounds for the execution time that the analysed programs will ever take during operation. The range of analysis approaches used include static, measurement-based and probabilistic methods, as well as hybrid combinations of them. Each of those approaches delivers its results on the assumption that certain hypotheses hold on the timing behaviour of the system as well that the user is able to provide the needed input information. Often enough the trustworthiness of those methods is only adjudged on the basis of the soundness of the method itself. However, trustworthiness rests a great deal also on the viability of the assumptions that the method makes on the system and on the user's ability, and on the extent to which those assumptions hold in practice. This paper discusses the hypotheses on which the major state-of-the-art timing analyses methods rely, identifying pitfalls and challenges that cause uncertainty and reduce confidence on the computed WCET estimates. While identifying weaknesses, this paper does not wish to discredit any method but rather to increase awareness on their limitations and enable an informed selection of the technique that best fits the user needs.","PeriodicalId":328716,"journal":{"name":"10th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115516888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 99
A model-based workflow from specification until validation of timing requirements in embedded software systems 嵌入式软件系统中基于模型的工作流,从规范到时间需求的验证
10th IEEE International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2015-06-08 DOI: 10.1109/SIES.2015.7185056
Arne Noyer, Padma Iyenghar, E. Pulvermüller, Joachim Engelhardt, Florian Pramme, G. Bikker
{"title":"A model-based workflow from specification until validation of timing requirements in embedded software systems","authors":"Arne Noyer, Padma Iyenghar, E. Pulvermüller, Joachim Engelhardt, Florian Pramme, G. Bikker","doi":"10.1109/SIES.2015.7185056","DOIUrl":"https://doi.org/10.1109/SIES.2015.7185056","url":null,"abstract":"In embedded software engineering, timing requirements are among the foremost non-functional requirements that have to be fulfilled. Therefore, there are specialized tools for analyzing and validating the timing behavior in embedded software. On the other hand, Model Driven Development (MDD) is considered as the next paradigm shift to address the increasing complexity in embedded software development. Despite this paradigm shift, it is advantageous to use specialized Requirements Management (RM) tools for managing requirements. Thus, it is intuitive to perceive that a workflow for collaborating with RM, MDD and timing validation tools is very useful. Nevertheless, such a workflow is still missing. This paper addresses those gaps and proposes an approach towards an integrated workflow for managing timing requirements in RM tools, specifying them in MDD tools and their validation in tools for timing analyses.","PeriodicalId":328716,"journal":{"name":"10th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132110814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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