{"title":"Power gating in FinFET Adiabatic circuits","authors":"Nikhil Deo, Rusni Kima Mangang, K. Murugan","doi":"10.1109/ICGCCEE.2014.6922293","DOIUrl":"https://doi.org/10.1109/ICGCCEE.2014.6922293","url":null,"abstract":"In this paper, we have implemented power gating in FinFET based Adiabatic circuits. Power gating is a low power design technique used in circuits having standby/sleep mode. Again adiabatic logic has very low switching power dissipation than compared to CMOS logic, also when FinFET devices are used in place of MOSFET then power dissipation can be further reduced. So we have used the combination of all these techniques to design low power digital circuits. For validating our idea we designed two power gated adiabatic circuits, first one is IPFAL Inverter and the second one is IPFAL 2:1 Multiplexer using PTM 45nm technology node for bulk MOSFET as well as FinFET.","PeriodicalId":328137,"journal":{"name":"2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129133557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analysis of the performance of an MRAS based sensorless speed estimation scheme for induction motors under fluctuating inputs","authors":"C. Nagamani, Nikhilesh Prasannakumar, R. Raju","doi":"10.1109/ICGCCEE.2014.6922458","DOIUrl":"https://doi.org/10.1109/ICGCCEE.2014.6922458","url":null,"abstract":"A sensorless speed estimation scheme for a three phase squirrel cage induction machine is investigated in this paper. The Model Reference Adaptive Scheme (MRAS) based sensorless speed estimator uses the error in instantaneous reactive power for speed estimation. The Q-MRAS based method is computational simple and its closed loop nature reduces steady state errors. The performance of the speed estimator under changes in load torque, fluctuations in supply voltage and frequency and under the presence of unbalance and harmonics are investigated using MATLAB simulations. The Q-MRAS based scheme is found to be quite robust under all conditions, with almost no steady state error and transient errors less than 3%.","PeriodicalId":328137,"journal":{"name":"2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133775501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design and implementation of multi-rate LDPC decoder for IEEE 802.16e wireless standard","authors":"Vijaya Kumar, R. Shrestha, R. Paily","doi":"10.1109/ICGCCEE.2014.6922226","DOIUrl":"https://doi.org/10.1109/ICGCCEE.2014.6922226","url":null,"abstract":"In this paper, a flexible architecture of multi-rate Low Density Parity Check (LDPC) decoder has been presented. It supports six different code-rates which are specified by IEEE 802.16e wireless standard. In the suggested decoder-architecture, column layered decoding technique has been employed to increase the convergence speed. Additionally, the decoder-design incorporates parallel architecture to achieve higher throughput which meets the requirement of IEEE 802.16e standard. An Application Specific Integrated Circuits (ASIC) implementation of this decoder-architecture has been performed at 130 nm Complementary Metal Oxide Semiconductor (CMOS) technology node. At the worst-case Process Voltage Temperature (PVT) corner with the supply voltage of 1.08 V, the implemented decoder has achieved a maximum information throughput of 159.6 Mbps at a clock frequency of 39.9 MHz.","PeriodicalId":328137,"journal":{"name":"2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133516820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Application of fireflies algorithm to solve economic load dispatch","authors":"G. Kannan","doi":"10.1109/ICGCCEE.2014.6922317","DOIUrl":"https://doi.org/10.1109/ICGCCEE.2014.6922317","url":null,"abstract":"This paper presents a new algorithm called Firefly Algorithm to solve the well-known power system Economic load dispatch problem. Firefly Algorithm is a novel nature-inspired algorithm inspired by social behavior of fireflies and the phenomenon of bioluminescent communication between them. Our proposed algorithm utilized fireflies food searching mechanism to optimize economic load dispatch problem in power system. This makes the algorithm more convergence and less complexity. It is also appropriate for high-speed real-time application due to fast and less execution time. In order to demonstrate the effectiveness of the proposed algorithm has been tested with the standard 6-bus, IEEE-14 bus and IEEE-30 bus system with several heuristic load patterns. The numerical result reveals that the proposed algorithm can provide appreciably better solutions within reasonable time.","PeriodicalId":328137,"journal":{"name":"2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131567013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. V. Ajith Krishnan, Nikhil Tomson, C. John, S. Navya
{"title":"A microcontroller based five phase BLDC motor drive","authors":"R. V. Ajith Krishnan, Nikhil Tomson, C. John, S. Navya","doi":"10.1109/ICGCCEE.2014.6922423","DOIUrl":"https://doi.org/10.1109/ICGCCEE.2014.6922423","url":null,"abstract":"Brushless motors, which finds diverse applications in industries and automation systems, combine high reliability with high efficiency at a lower cost in comparison with the conventional brushed motors. The reliability and efficiency can be further improved by incorporating a multiphase design which however increases the system cost and the inverter circuit complexity. This paper proposes a five phase brushless dc motor drive and describes how a AT89C51 microcontroller can be used to drive it. The design and the MATLAB/SIMULINK model of the proposed five phase BLDC motor and its driving circuit is discussed and the results are presented.","PeriodicalId":328137,"journal":{"name":"2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134091655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Loop slope adjustment methods for the control of Automatic Voltage Regulator","authors":"Srikanth Malladi, K. Swaroop, Omkar Koduri","doi":"10.1109/ICGCCEE.2014.6922287","DOIUrl":"https://doi.org/10.1109/ICGCCEE.2014.6922287","url":null,"abstract":"This paper explores well known PID tuning algorithms based on loop slope adjustment and its application to the control of Automatic Voltage Regulator for both set point tracking and disturbance rejections. Four different PID tuning algorithm viz. Zeigler Nichols Method, Modified Ziegler-Nichols, Bode's Integral based method and Flat phase method were considered. Each of these methods gives a new approach to relate Ti and Td apart from achieving desired specifications. Performance comparison was carried out considering some well known performance criteria.","PeriodicalId":328137,"journal":{"name":"2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134287345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Compensation of dispersion in 5 Gbps WDM system by using DCF","authors":"Anith Mohan, N. Saranya, S. Johnson, A. Sangeetha","doi":"10.1109/ICGCCEE.2014.6922229","DOIUrl":"https://doi.org/10.1109/ICGCCEE.2014.6922229","url":null,"abstract":"In Optical communication network pulse broadening due to chromatic dispersion becoming an important factor for signal degradation. This may become worse when the data transmission rate keep increasing. So in order to achieve high data transmission rate at long span-length light wave system, the chromatic dispersion in the fiber must be compensated. Many compensation techniques have been demonstrated and they exhibit a variety of different and often complimentary properties. Transmitter compensation techniques are the most easily implemented but provide a limited amount of compensation. The most commercially advanced technique is negative dispersion fiber. We discuss the design of a Wavelength Division Multiplexed system (WDM) with dispersion compensation fiber (DCF). The effect of both pre-compensation and post-compensation techniques has also been discussed. The bit error rate (BER) of the system under two different modulation schemes is also discussed and identifies the better modulation format and best compensation technique in WDM network.","PeriodicalId":328137,"journal":{"name":"2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133290429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hybrid framework for face recognition with expression & illumination variations","authors":"K. V. Krishna Kishore, G. Varma","doi":"10.1109/ICGCCEE.2014.6921408","DOIUrl":"https://doi.org/10.1109/ICGCCEE.2014.6921408","url":null,"abstract":"In this paper, a hybrid framework is proposed to improve the performance of face recognition by combining global descriptors and local appearance descriptors and proved that their complementary nature makes them good candidates in the better recognition of faces. The proposed face recognition method can handle facial appearance variations which are caused by facial expression and illumination under controlled capture conditions. Different from traditional face recognition methods, the proposed method uses multiple features which are extracted using Global and Local feature extraction algorithms like Principal Component Analysis (PCA) & Local Binary Pattern (LBP). Wavelet fused feature vector has richer information than feature vector extracted using unifeature extraction algorithms. Radial Basis Function (RBF) is used to classify feature vectors. The proposed method has been extensively evaluated on the standard benchmark databases like ORL and Grimace. It is found that significant results obtained in comparison with well-known generic face recognition methods.","PeriodicalId":328137,"journal":{"name":"2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133354867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kinattingal Sundareswaran, Kiran Kuruvinashetti, P. S. R. Nayak
{"title":"Application of Particle Swarm Optimization for output voltage regulation of dual input buck-boost converter","authors":"Kinattingal Sundareswaran, Kiran Kuruvinashetti, P. S. R. Nayak","doi":"10.1109/ICGCCEE.2014.6922312","DOIUrl":"https://doi.org/10.1109/ICGCCEE.2014.6922312","url":null,"abstract":"Dual input DC-DC converters act as an interface between different renewable energy sources and a common load. With uncertainty looming large over the renewable energy sources, it is mandatory to control the dual input DC-DC converter to provide a constant voltage to the load. This work reports the design and development of a Particle Swarm Optimization (PSO) based strategy for estimation of optimal controller structure for output voltage regulation of Dual input Buck-Boost (DIBB) converter. Computed and measured results at different operating points of DIBB suggest that the PSO tuned feedback controller is far superior to its conventional counterpart in delivering the desired output voltage with excellent dynamic response.","PeriodicalId":328137,"journal":{"name":"2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132117471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low-complexity systolic design for finite field multiplier","authors":"T. P. Rajalakshmi, C. B. Rajesh","doi":"10.1109/ICGCCEE.2014.6922224","DOIUrl":"https://doi.org/10.1109/ICGCCEE.2014.6922224","url":null,"abstract":"Here focus, is to implement a polynomial basis finite field multiplier. An area efficient systolic structure for finite field multiplication over the galois field GF(2m) based on irreducible polynomial was introduced. A novel cutest retiming can be introduced to reduce the critical path and thereby reduce the latency of operation. From the synthesis result from synopsys design vision and Xilinx, we find that the complexity of structure in terms of area, power and latency of the proposed structure can be reduced from the existing design.","PeriodicalId":328137,"journal":{"name":"2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122941026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}