Design and implementation of multi-rate LDPC decoder for IEEE 802.16e wireless standard

Abstract

In this paper, a flexible architecture of multi-rate Low Density Parity Check (LDPC) decoder has been presented. It supports six different code-rates which are specified by IEEE 802.16e wireless standard. In the suggested decoder-architecture, column layered decoding technique has been employed to increase the convergence speed. Additionally, the decoder-design incorporates parallel architecture to achieve higher throughput which meets the requirement of IEEE 802.16e standard. An Application Specific Integrated Circuits (ASIC) implementation of this decoder-architecture has been performed at 130 nm Complementary Metal Oxide Semiconductor (CMOS) technology node. At the worst-case Process Voltage Temperature (PVT) corner with the supply voltage of 1.08 V, the implemented decoder has achieved a maximum information throughput of 159.6 Mbps at a clock frequency of 39.9 MHz.