{"title":"Quantitative analysis of Carotid atherosclerosis to predict the severity of stroke","authors":"S. Maheswari, D. Senthilbabu","doi":"10.1109/ICGCCEE.2014.6922403","DOIUrl":"https://doi.org/10.1109/ICGCCEE.2014.6922403","url":null,"abstract":"Stroke is the third leading cause of death in the World. It occurs usually when the blood supply to parts of the brain is suddenly interrupted due to the accumulation of blood cell, lipid, protein and cholesterol crystals (called as plaques) in the Carotid arteries which blocks the oxygen supply to the part of the brain cells, and these cells will eventually begin to die. A plaque characteristic on texture and ecogenicity helps to identify a vulnerable and non vulnerable plaque which aids the physician to provide required therapy. Carotid artery image is considered as an input. The high resolution carotid artery image is fed as an input to the feature extraction. The parameters calculated from the feature extraction are energy, standard deviation, correlation co-efficient, mean and entropy. Neural network classifier is used to compare the trained image and input image based on score value. Percentage of lumen area occupied by the arthromatous material (Degree of Stenosis) can be identified by measuring the thickness of the plaque. This enables us to predict the severity of the stroke.","PeriodicalId":328137,"journal":{"name":"2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127214423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Performance analysis of mobile patient network using AODV and DSR routing algorithms","authors":"R. Tiwari, S. Shrivastava, Susmita Das","doi":"10.1109/ICGCCEE.2014.6922450","DOIUrl":"https://doi.org/10.1109/ICGCCEE.2014.6922450","url":null,"abstract":"In the case of medical applications, the main requirement is to improve the control overhead and to achieve the reliable data transmission. A ZigBee based mobile patient monitoring network model is proposed, and its performance improvement is analysed based on reduced delay and enhanced throughput. We are focusing on the separate and comparative performance evaluation of AODV and DSR routing protocol in a wireless body area network (WBAN). WBAN has numbered of the sensor nodes for collecting the physiological status of patients like ECG, temperature, Heartbeat, etc. Mobile sensor nodes forming an unpredictable topology and link instability that make routing protocols a core issue. In this paper, we considered one wireless network having the hospital care center who monitors mobile patient under AODV and DSR routing protocols, and transmits data to various nodes. Simulation has been performed using OPNET simulation tool, and the results demonstrate that the AODV routing protocol is best suited for medical monitoring system.","PeriodicalId":328137,"journal":{"name":"2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131788168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An advanced low complexity double error correction of an BCH decoder","authors":"M. Prashanthi, Damarla Paradhasaradhi, N. Vivek","doi":"10.1109/ICGCCEE.2014.6922218","DOIUrl":"https://doi.org/10.1109/ICGCCEE.2014.6922218","url":null,"abstract":"Bose, Ray-Chaudhuri, Hocquenghem (BCH) codes are one of the efficient error-correcting codes used to correct errors occurred during the transmission of the data in the unreliable communication mediums. This paper presents a low-complexity and area efficient error-correcting BCH decoder architecture for detecting and correction of two errors. The advanced Peterson error locator computation algorithm, which significantly reduces computational complexity, is proposed for the IBM block in the BCH decoder. In addition, a modified syndrome calculator and chien search are proposed to reduce hardware complexity. The proposed model and design techniques have considerably less hardware complexity and latency than those using conventional algorithms. For a (15,7) BCH decoder over GF(4), the proposed design can lead to a reduction in complexity of at least 30 % compared to conventional architectures. The enhanced chase BCH decoder is designed using hardware description language called Verilog and synthesized in Xilinx ISE 13.2.","PeriodicalId":328137,"journal":{"name":"2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133074248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Probabilistic approach based optimal placement of phasor measurement units via the estimation of dynamic vulnerability assessment","authors":"M. Priyadharshini, R. Meenakumari, P. Scholar","doi":"10.1109/ICGCCEE.2014.6922429","DOIUrl":"https://doi.org/10.1109/ICGCCEE.2014.6922429","url":null,"abstract":"This paper aims in presenting the optimal placement of the Phasor Measurement Unit (PMU) of an IEEE-5 bus system. In this paper a simplest scheme for dynamic vulnerability assessment based on Power System Loss Index has been proposed for Optimal PMU placement and which is compared against the Multi Criteria Decision Making (MCDM) Techniques namely Analytical Hierarchy Process (AHP), Fuzzy AHP approach and Technique for Order Preference by Similarity to Ideal Solution (TOPSIS) approach. MCDM helps in finding the best solution among the multiple alternatives for the placement of PMU which is based on the weighing factor. But this MCDM has neglected the dynamic operation of the system. In the proposed scheme, the probabilistic nature of network dynamics is performed by Monte Carlo Simulation to iteratively evaluate the system performance for probable input parameter variations such as load variation, generation variation and list of credible contingencies to assess the vulnerability index of the system. Newton - Raphson load flow analysis is performed for each contingency and the power system losses in various parts of the networks are observed. The vulnerability Index is calculated based on total Power System Loss (PSL). Based on the index, the vulnerable regions in the power system network are identified and clustered with the help of Data clustering algorithm. The PMUs have to be located in the most vulnerable regions to prevent the system from blackouts and to take corrective control actions. This proposed simple approach is tested on IEEE-5 Bus test systems. The test result shows that PSL index is effective in identifying the vulnerable regions for optimal PMU placement. The findings of the PMU location are compared against MCDM techniques.","PeriodicalId":328137,"journal":{"name":"2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126759424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of matrix converter based dynamic voltage restorer for power quality enhancement","authors":"S. Nandagopal, R. Subramanian","doi":"10.1109/ICGCCEE.2014.6922387","DOIUrl":"https://doi.org/10.1109/ICGCCEE.2014.6922387","url":null,"abstract":"A new series power conditioning system using a matrix converter is proposed. The proposed solution has utilized a single AC/AC power converter for interface as an conventional AC/DC/AC converter. The dynamic model is used to design a vector control system that seamlessly integrates functional of compensating load voltage and managing energy storage during voltage sag and idling modes. The purpose of matrix converter used in dynamic voltage restorer (DVR) for power quality enhancement, which is connected in between the feeder to secure the electric power from sags. The DVR is based on dqo algorithm which is discussed with matrix converter to inject external supply into the feeder by means of a series transformer. Harmonics are produced due to non-linear loads, and it is filtered out by a filter which is connected at terminal end of the system. The simulation results are carried out by MATLAB and the performance of proposed method is verified.","PeriodicalId":328137,"journal":{"name":"2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131490755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pratik K. Pasiyawala, M. Patel, Y. Patel, Unnati J. Patel
{"title":"Performance analysis of error concealment algorithm during image recovery","authors":"Pratik K. Pasiyawala, M. Patel, Y. Patel, Unnati J. Patel","doi":"10.1109/ICGCCEE.2014.6922451","DOIUrl":"https://doi.org/10.1109/ICGCCEE.2014.6922451","url":null,"abstract":"Generally, transmission of raw image requires very high bit rates. To reduced bit rate, compression of raw image using block base coding is necessary. Further these blocks are transmitted packet by packet on transmission line but it may happen that some packets may be loss during transmission. Due to loss of packets, receiver will produced corrupted image with missing blocks, which will reduce image quality. To recover missing blocks and improve image quality, error concealment technique been used. This paper shows the performance analysis of Error Concealment (EC) technique for different lost block size (4×4, 8×8, and 16×16). Experimental results demonstrate that error concealment technique provides better improvements in PSNR (dB) and SSIM for small lost block size, which clearly indicates that EC method able to recover small lost block size more efficiently compared to large lost block size.","PeriodicalId":328137,"journal":{"name":"2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129436566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"TCAD based study of a noble 24 nm DMIDG MOSFET for LOW power applications","authors":"Soumen Deb, S. Baishya","doi":"10.1109/ICGCCEE.2014.6921414","DOIUrl":"https://doi.org/10.1109/ICGCCEE.2014.6921414","url":null,"abstract":"This paper presents the design of a noble 24 nm asymmetric Dual gate Material (for NMOS/PMOS) Independent Double Gate (DMIDG) with elevated S/D Structure, Buried Polysilicon Back Gate, High-K dielectric spacer, High-K gate stack of HfO2 over SiO2 thin layer (SiO2 thickness being 0.85 nm while maintaining an EOT of 1.2 nm) at front gate in order to suppress SCE's. An IDG MOS device with metallic gate and lightly Doped Channel (of doping concentration of 2×109 cm-3) provides better leakage performance with the cost of effective high threshold voltage (0.56V for NMOS and -0.49V for PMOS), with symmetrical ID-VGS Characteristics and almost symmetrical ID-VDS characteristics for both NMOS and PMOS devices. The proposed devices are found to possess quite low Miller Capacitance (~0.12 fF/μm for PMOS and ~0.125 fF/μm for NMOS) with metallic front gate and lightly doped channel structure. The device also shows considerably low total gate capacitance as compared to ITRS Specification for LSTP application even in quasi Ballistic regime of channel length up to 12 nm. A CMOS inverter constructed using such DMIDG MOS devices shows quite low inverter delay of ~ 4 psec. with back gate biasing of 0V for both PMOS and NMOS devices of channel length 24 nm. The delay Characteristics are also being modulated by favorable back gate biasing techniques. The inverter delay is found to be reduced following the technology downscaling and is close to ITRS Specifications. The dynamic energy consumption of the inverter is also low at favorable back gate biasing (of 0.5V for NMOS and -0.5V for PMOS) viz. 0.35 fJ/μm and it goes on diminishing as channel length goes on reducing. IDG MOS devices with metallic gate and lightly doped show better inverter characteristics in comparison to Polysilicon front gate and undoped channel devices.","PeriodicalId":328137,"journal":{"name":"2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132647184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Seven level inverter with nearest level control","authors":"Megha S. Varna, Jenson Jose","doi":"10.1109/ICGCCEE.2014.6922346","DOIUrl":"https://doi.org/10.1109/ICGCCEE.2014.6922346","url":null,"abstract":"Multilevel inverters are commonly used for high power applications. The structure of a multilevel inverter is to synthesize sinusoidal waveform from several levels of voltages. This paper deals with a novel seven level cascaded multilevel inverter. Almost all the drawbacks of the conventional multilevel inverters is rectified by the proposed topology. This topology uses less number of switches as compared with conventional topology, where it reduces the complexity and overall size of the system which in turn reduces the harmonics and cost of the entire system. Fewer switches will be conducting for specific time intervals so switching loss is also reduced in the proposed topology. A seven level inverter simulation is carried with the implementation of nearest level control. The proposal is validated by extensive simulation studies.","PeriodicalId":328137,"journal":{"name":"2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127591282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The design approach for fast computation of fourier transform over a finite field","authors":"Tejaswini P. Deshmukh, Vrushali P. Dewalkar","doi":"10.1109/ICGCCEE.2014.6922465","DOIUrl":"https://doi.org/10.1109/ICGCCEE.2014.6922465","url":null,"abstract":"The Fast Fourier Transform can be determined in Complex field and Galois field. The paper suggests the algorithm for finding Fast Fourier Transform over a Galois field. This method uses the advantage of cyclotomic decomposition. Basically decomposition of the original polynomial into a sum of linearized polynomial is done and then evaluated at a set of basis points. The idea of architecture is also proposed. The architecture is composed of two main units principle unit and additional unit. This Fast Fourier Transform methods can be capably used in implementations of discrete Fourier transforms over finite field, which have extensive applications in cryptography and error control codes. The method is becoming popular because of its low computational complexity.","PeriodicalId":328137,"journal":{"name":"2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122879944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Aruna, A. Dhivya Parameswari, M. Malini, G. Gopu
{"title":"Voice recognition and touch screen control based wheel chair for paraplegic persons","authors":"C. Aruna, A. Dhivya Parameswari, M. Malini, G. Gopu","doi":"10.1109/ICGCCEE.2014.6922215","DOIUrl":"https://doi.org/10.1109/ICGCCEE.2014.6922215","url":null,"abstract":"The wide spread prevalence of lost limbs and sensing system is of major concern in present day due to accident, age and health problems. To assist people with such defects, the proposed intelligent wheelchair system uses dual control for navigation in familiar environments. The two modes of input control to the wheelchair are voice recognition and touch screen. When one want to change the direction, the touch screen sensor is modelled by pressing finger against the various quadrants on the touch screen, which has different values programmed for different direction. This can also be controlled through simple voice commands using voice controller. By storing a single letter in voice recognition kit for each direction control, the recognition time is reduced drastically and thus quick reach to destination is obtained. The wheelchair consists of DC brushless motors at the rear end and it is controlled by using PWM technique. A brake control mechanism is included to control the wheelchair. From previous literature surveys observed, the accuracy of the touch screen was found to be 50%. In this proposed system achievement of wheelchair movement in all direction is obtained with an accuracy of 94.6%. Voice recognition has accuracy of 80.8% which is 30% higher than the study done by Prathyusha et al. This device helps the disabled to have automatic advancement to their destination through predefined paths in the indoor system.","PeriodicalId":328137,"journal":{"name":"2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115284562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}