Low-complexity systolic design for finite field multiplier

Abstract

Here focus, is to implement a polynomial basis finite field multiplier. An area efficient systolic structure for finite field multiplication over the galois field GF(2m) based on irreducible polynomial was introduced. A novel cutest retiming can be introduced to reduce the critical path and thereby reduce the latency of operation. From the synthesis result from synopsys design vision and Xilinx, we find that the complexity of structure in terms of area, power and latency of the proposed structure can be reduced from the existing design.