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2007 International Symposium on Semiconductor Manufacturing最新文献

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Key factors to suppress thickness variation in MOCVD HfSiON-Films 抑制MOCVD hfsion膜厚度变化的关键因素
2007 International Symposium on Semiconductor Manufacturing Pub Date : 2007-10-01 DOI: 10.1109/ISSM.2007.4446844
I. Yamamoto, Y. Kato
{"title":"Key factors to suppress thickness variation in MOCVD HfSiON-Films","authors":"I. Yamamoto, Y. Kato","doi":"10.1109/ISSM.2007.4446844","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446844","url":null,"abstract":"We investigated the deposition process reproducibility of extremely-thin (<1 nm) HfSiON-films deposited in a batch-type reactor. The deposition-rate measured on a monitor-wafer appeared to be affected by the base-oxide thickness, substrate doping and the surface material of the monitor-wafer. Furthermore, the deposition-rate is found to be affected also by the surface material of the back-surface of its adjacent wafer. Precise control of these factors is essential for good reproducibility.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130588660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Perspectives on integrated metrology and wafer-level control 集成计量与晶圆级控制展望
2007 International Symposium on Semiconductor Manufacturing Pub Date : 2007-10-01 DOI: 10.1109/ISSM.2007.4446829
K. Lensing, B. Stirton
{"title":"Perspectives on integrated metrology and wafer-level control","authors":"K. Lensing, B. Stirton","doi":"10.1109/ISSM.2007.4446829","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446829","url":null,"abstract":"In this paper, we will discuss the critical factors that are driving the implementation progress of integrated metrology (IM) and wafer-level advanced process control (APC). We will describe the potential benefits of IM and the engineering roadblocks that have limited the realization of those benefits. Finally, we will describe AMD's approach to solving the wafer-level control problem by using stand-alone metrology, dynamic wafer sampling, and a bias correction algorithm.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134444686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
The effects of small lot manufacturing on AMHS operation and equipment front-end design 小批量生产对AMHS运行及设备前端设计的影响
2007 International Symposium on Semiconductor Manufacturing Pub Date : 2007-10-01 DOI: 10.1109/ISSM.2007.4446800
O. Zimmerhackl, J. Rothe, K. Schmidt, L. Marshall, A. Honold
{"title":"The effects of small lot manufacturing on AMHS operation and equipment front-end design","authors":"O. Zimmerhackl, J. Rothe, K. Schmidt, L. Marshall, A. Honold","doi":"10.1109/ISSM.2007.4446800","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446800","url":null,"abstract":"This paper analyzes the effects of small lot manufacturing (SLM) on equipment operation and fab performance. It also discusses equipment front-end design challenges and describes options for carrier handling and AMHS operation to maximize the productivity benefits of small lot manufacturing. This paper focuses primarily on the material handling aspects of SLM and as such, does not discuss the influences of equipment Setup or First Wafer Delay which have been covered in other related publications.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133184273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Automated statistical process matching across the virtual fab 自动统计过程匹配整个虚拟工厂
2007 International Symposium on Semiconductor Manufacturing Pub Date : 2007-10-01 DOI: 10.1109/ISSM.2007.4446838
G. Nirgude, D. Nassar
{"title":"Automated statistical process matching across the virtual fab","authors":"G. Nirgude, D. Nassar","doi":"10.1109/ISSM.2007.4446838","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446838","url":null,"abstract":"Statistical process matching plays a central role in detecting and minimizing special and common cause variations in semiconductor manufacturing. Performing automated statistical matching across many fabs, thousands of tools and millions of data points at acceptable performance and scalability requires a complex automation infrastructure. In this paper, we cover the main features of Intel's fab automation infrastructure that facilitates a multitude of offline statistical analyses.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129355504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Manufacturing challenges and method of fabrication of on-chip capacitive digital isolators 片上电容式数字隔离器的制造挑战和制造方法
2007 International Symposium on Semiconductor Manufacturing Pub Date : 2007-10-01 DOI: 10.1109/ISSM.2007.4446870
P. Mahalingam, D. Guiling, S. Lee
{"title":"Manufacturing challenges and method of fabrication of on-chip capacitive digital isolators","authors":"P. Mahalingam, D. Guiling, S. Lee","doi":"10.1109/ISSM.2007.4446870","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446870","url":null,"abstract":"A robust and innovative method of fabrication of on-chip capacitive digital isolators integrated in a high precision analog CMOS process is presented in this paper. Several dielectric materials such as TEOS, HDP, silicon nitride, silicon oxynitride, with different film stresses were evaluated for this capacitor in order to achieve the high breakdown voltage (RMS and surge) requirements of the isolation capacitor while ensuring wafer manufacturability. Impact of various integration schemes and combinations of the dielectric layers on the capacitor breakdown voltage performance along with a package and wafer-level reliability assessment of these integration schemes is discussed.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131364893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Impact of lot release strategies on ‘make-to-order’ production line performance 批放行策略对“按订单生产”生产线性能的影响
2007 International Symposium on Semiconductor Manufacturing Pub Date : 2007-10-01 DOI: 10.1109/ISSM.2007.4446809
S. Murray, P. Young, J. Geraghty, S.S. Sievwright
{"title":"Impact of lot release strategies on ‘make-to-order’ production line performance","authors":"S. Murray, P. Young, J. Geraghty, S.S. Sievwright","doi":"10.1109/ISSM.2007.4446809","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446809","url":null,"abstract":"This paper examines the relationship between lot release variability and queuing time in a simple six operation manufacturing process line operating under a push-type lot release policy. Five different lot release strategies are modelled, based on two different operation capacity scenarios. The performance resulting from the departure variability caused by each of the release strategies is analyzed, as well as the queuing impact due to capacity.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"215 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116369165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Novel patterning shrink technique enabling sub-50 nm trench and contact integration 新颖的图案收缩技术，使低于50纳米的沟槽和接触集成
2007 International Symposium on Semiconductor Manufacturing Pub Date : 2007-10-01 DOI: 10.1109/ISSM.2007.4446855
S. Demuynck, Z. Tokei, C. Zhao, J. de Marneffe, H. Struyf, W. Boullart, M. O. de Beeck, L. Carbonell, N. Heylen, J. Vaes, G. Beyer, S. Vanhaelemeersch, R. Sadjadi, H. Zhu, P. Cirigliano, J.S. Kim, J. Vertommen, B. Coenegrachts, E. Pavel, A. Athayde
{"title":"Novel patterning shrink technique enabling sub-50 nm trench and contact integration","authors":"S. Demuynck, Z. Tokei, C. Zhao, J. de Marneffe, H. Struyf, W. Boullart, M. O. de Beeck, L. Carbonell, N. Heylen, J. Vaes, G. Beyer, S. Vanhaelemeersch, R. Sadjadi, H. Zhu, P. Cirigliano, J.S. Kim, J. Vertommen, B. Coenegrachts, E. Pavel, A. Athayde","doi":"10.1109/ISSM.2007.4446855","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446855","url":null,"abstract":"In this paper we demonstrate the feasibility of integrating a technique for shrinking the lithography-defined feature size by using a plasma process prior to etch. The technique is based on a sequential deposition and selective removal of a polymer coating formed on the top and sidewalls of the developed resist. This method can be applied to both contacts and trenches and allows tuning of the shrink amount. Yielding damascene trenches down to 45 nm were obtained, shrunk from a 85 nm print, while functional 100 nm contacts were formed starting from a 150 nm print. In both cases excellent within-wafer non-uniformities were achieved.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131296614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Eliminating uT induced memory fails through waferless auto clean 通过无晶圆片自动清洗消除uT诱导内存故障
2007 International Symposium on Semiconductor Manufacturing Pub Date : 2007-10-01 DOI: 10.1109/ISSM.2007.4446895
Goa Yee Boon, S. Teo, Au Hing Ho, D. Leong
{"title":"Eliminating uT induced memory fails through waferless auto clean","authors":"Goa Yee Boon, S. Teo, Au Hing Ho, D. Leong","doi":"10.1109/ISSM.2007.4446895","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446895","url":null,"abstract":"In this paper, micro trenching (muT) on silicon substrate caused by the poly gate etch process, was found to be the root cause of memory bin failures (MBIST) in our 0.15 mum devices. Through advanced FA techniques using CAFM (conductive atomic force microscopy) & nano probing, we found that the micro trenching MBIST failures occurs primarily due abnormal leakage across the gate due gate oxide damage next to the micro trench. In severe cases transconductance degradation of the Pass gate (PG) transistor was observed. We discovered the micro trenching phenomena was due to 'cold' poly etcher chamber effect. A novel method by running Pre-WAC (waferless auto clean) using the O2 and SF6 gas before polysilicon etch was found to be effective in eliminating the fails.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129767022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Laser processing of doped silicon wafer by the Stealth Dicing 隐形切割掺杂硅片的激光加工
2007 International Symposium on Semiconductor Manufacturing Pub Date : 2007-10-01 DOI: 10.1109/ISSM.2007.4446877
M. Kumagai, T. Sakamoto, E. Ohmura
{"title":"Laser processing of doped silicon wafer by the Stealth Dicing","authors":"M. Kumagai, T. Sakamoto, E. Ohmura","doi":"10.1109/ISSM.2007.4446877","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446877","url":null,"abstract":"Stealth dicing has outstanding advantages over conventional dicing methods such as blade dicing and laser ablation method. Therefore, stealth dicing is being already used for the wafer manufacturing, and the process started to be spread in the market. In this paper, the relationship between absorption coefficient and resistivity which is the most important property for the stealth dicing were explained. Starting from the case study about the processing phenomenon of wafers with different resistivity, the relationship between resistivity and absorption coefficient was assumed by an equation. The reached beam energy at the focal point was estimated by using absorption coefficient that was calculated from above estimated equation. When the reached beam energy was equal to each other, similar SD layers were generated, however, the separation ability did not only depend on the energy itself.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129340233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Process and chamber health monitoring of plasma enhanced ti deposition process through high performance VI-probe 利用高性能vi探针监测等离子体增强钛沉积过程和腔室健康
2007 International Symposium on Semiconductor Manufacturing Pub Date : 2007-10-01 DOI: 10.1109/ISSM.2007.4446841
K. Baek, B. Coonan, M. Carbery, Jinkyung Joo, Hyunsoo Woo, Tae Soon Lee, Hyeon Soo An, Yoonbon Koo, Cheonsu Han, Sung-Jae Han, Yongjin Kim, Seong-woon Choi, W. Han
{"title":"Process and chamber health monitoring of plasma enhanced ti deposition process through high performance VI-probe","authors":"K. Baek, B. Coonan, M. Carbery, Jinkyung Joo, Hyunsoo Woo, Tae Soon Lee, Hyeon Soo An, Yoonbon Koo, Cheonsu Han, Sung-Jae Han, Yongjin Kim, Seong-woon Choi, W. Han","doi":"10.1109/ISSM.2007.4446841","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446841","url":null,"abstract":"As an alternative to plasma sensors, high performance VI probe was evaluated in a plasma enhanced Ti deposition process. Its utilization was focused on finding any reasonable differences between good and bad chambers classified in terms of end of line yield data. Some differences of delivered power and time trace current signal between chambers were found, which well matches the good and bad chamber classification. Also, a fault detection and classification algorithm to handle huge amount of raw VI-probe data was evaluated. The algorithm estimates deviation of TiCl4 content in plasma occurs right after preventive maintenance, which might be considered as a chamber conditioning procedure. Despite requiring additional evaluations, the combination of VI-probe and well-developed algorithm might be a feasible solution where conventional plasma sensors can not be applied.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129441102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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