2016 Fourth International Symposium on Computing and Networking (CANDAR)最新文献

{"title":"A Minimum Contention Window Control Method for Lowest Priority Based on Collision History of Wireless LAN","authors":"Tomoki Hanzawa, S. Kimura","doi":"10.1109/CANDAR.2016.0056","DOIUrl":"https://doi.org/10.1109/CANDAR.2016.0056","url":null,"abstract":"Because of the widespread adoption of mobile devices, many applications have provided support for wireless LAN (WLAN). Under these circumstances, one of the important issues is to provide good quality of service (QoS) in WLAN. For this purpose, Dhurandher et al. improved the distributed coordination function (DCF). In this method, the contention window (CW) is divided into multiple ranges. Each range is independent of all other ranges and is assigned to a different priority. Although the highest-priority throughput increased using this method, throughput for the other priorities significantly decreased. To overcome this problem, this paper proposes a minimum contention window control method for two (high and low) priorities. In the method, all nodes are assumed to use real-time applications or data transmission. The former real-time frames are high priority and are sent by UDP. The latter data frames are low priority and are sent by TCP. The purpose of the proposed method is not only to provide good QoS for the highest priority but also to prevent decreasing the QoS for other priorities in WLAN. For this purpose, the proposed method keeps the CW for the high priority at a low value and controls the CW for the low priority based on the collision history. Finally, the network simulations demonstrated that the proposed method reduces the decrease in the average total throughput of the low priority frames as well as reducing the packet drop rate of both priorities, compared with those for DCF and Dhurandher's method.","PeriodicalId":322499,"journal":{"name":"2016 Fourth International Symposium on Computing and Networking (CANDAR)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122257686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Rapid Verification Framework for Developing Multi-core Processor","authors":"Kouki Kayamuro, Takahiro Sasaki, Y. Fukazawa, T. Kondo","doi":"10.1109/CANDAR.2016.0074","DOIUrl":"https://doi.org/10.1109/CANDAR.2016.0074","url":null,"abstract":"A multi-core processor is widely used to achieve both high performance and low energy consumption. However, verification of a multi-core processor is more difficult than that of single-core processor. Because multi-core processor has large and complex circuits, and special mechanisms such as a cache coherency mechanism also increases complexity. In general, design flow of a processor include such as the following steps; functional verification by high level language, cycle accurate verification by RTL simulation and timing analysis considered gate delay, wiring delay and others. In particular, co-simulation framework for single-core processor has been proposed to reduce time of cycle accurate verification with RTL simulation. However, if the conventional framework is applied to verify a multi-core processor, it causes three problems; failure of the co-simulation framework by a mismatch of load and store operation, failure of the system call emulation by cache coherency mechanism and requirement of task scheduling by execution multi-threaded program. These problems makes verification of a multi-core processor difficult seriously and increases simulation time dramatically. Therefore, this paper proposes a rapid verification framework to support execution of a multi-threaded program for multi-core processors. The proposed method makes it possible to verify both a homogeneous and heterogeneous multi-core processors with the cache coherency mechanism, and to execute multithreaded programs without full system simulation. The proposed framework extends conventional co-simulation framework for a single-core processor. The proposed framework is composed of the following three extensions; bypassing loaded value from the verified processor to virtual processor, a cache access mechanism for system call emulation, and an internal task scheduler. As evaluation results, our framework verifies two-core processor correctly. Furthermore, the proposed method achieves to reduce the number of execution cycles by 71% in maximum and 46% in average compared with full system simulation.","PeriodicalId":322499,"journal":{"name":"2016 Fourth International Symposium on Computing and Networking (CANDAR)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126913533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SQL Injection Attack Detection Method Using Expectation Criterion","authors":"Linghuan Xiao, Shinichi Matsumoto, Tomohisa Ishikawa, K. Sakurai","doi":"10.1109/CANDAR.2016.0116","DOIUrl":"https://doi.org/10.1109/CANDAR.2016.0116","url":null,"abstract":"SQL Injection attack is a kind of attack to a web application that accesses the database of the web application illegitimate. Along with the increasing use of web applications, the database where stores much sensitive information became more and more valuable and vulnerable. Eventually, SQL Injection attack has become rank one in top ten vulnerabilities as specified by Open Web Application Security Project (OWASP). In the other hand, although there was proposed a lot of methods to address the SQL injection attack, the current approaches almost have the limitation to detect full scope of the attack. What is more, the approaches have high precision in detecting pre-existing attacks though, but cannot detect unknown attacks. In this paper, we present an expectation-based solution to address SQL injection attack. Our proposal mainly has two phases. In the first phase, we calculate the occurrence probability of the SQL injection attack special characters in attack dataset and typical dataset respectively, and in the second phase we detect SQL injection attack base on expectation calculating take advantage of the computed occurrence probability.","PeriodicalId":322499,"journal":{"name":"2016 Fourth International Symposium on Computing and Networking (CANDAR)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114932341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Automated Dataset Construction from Web Resources with Tool Kayur","authors":"Alexander Kohan, M. Yamamoto, Cyrille Artho","doi":"10.1109/CANDAR.2016.0029","DOIUrl":"https://doi.org/10.1109/CANDAR.2016.0029","url":null,"abstract":"Many text mining tools cannot be applied directly to documents available on web pages. There are tools for fetching and preprocessing of textual data, but combining them in one working tool chain can be time consuming. The preprocessing task is even more labor-intensive if documents are located on multiple remote sources with different storage formats. In this paper we propose the simplification of data preparation process for cases when data come from wide range of web resources. We developed an open-sourced tool, called Kayur, that greatly minimizes time and effort required for routine data preprocessing steps, allowing to quickly proceed to the main task of data analysis. The datasets generated by the tool are ready to be loaded into a data mining workbench, such as WEKA or Carrot2, to perform classification, feature prediction, and other data mining tasks.","PeriodicalId":322499,"journal":{"name":"2016 Fourth International Symposium on Computing and Networking (CANDAR)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130606646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Cost-Effective and Scalable Merge Sorter Tree on FPGAs","authors":"T. Usui, Thiem Van Chu, Kenji Kise","doi":"10.1109/CANDAR.2016.0023","DOIUrl":"https://doi.org/10.1109/CANDAR.2016.0023","url":null,"abstract":"Sorting is an important computation kernel used in a lot of fields such as image processing, data compression, and database operation. There have been many attempts to accelerate sorting using FPGAs. Most of them are based on merge sort algorithm. Merge sorter trees are tree-structured architectures for large-scale sorting. If a merge sorter tree with K input leaves merges N elements, merge phases are performed recursively, so its time complexity is O(NlogK(N)). Hence, to achieve higher sorting performance, it is effective to increase the number of input leaves K. However, the hardware resource usage is O(K). It is difficult to efficiently implement a merge sorter tree with many input leaves. Ito et al. have recently proposed an algorithm which can reduce the hardware complexity of a merge sorter tree with K input leaves from O(K) to O(log(K)). However, they only report the evaluation results when K is 8 and 16. In this paper, we propose a cost-effective and scalable merge sorter tree architecture based on their algorithm. We show that our design achieves almost the same performance compared to the conventional design of which the hardware complexity is O(K). We implement a merge sorter tree with 1,024 input leaves on a Xilinx XC7VX485T-2 FPGA and show that the proposed architecture has 52.4x better logic slice utilization with only 1.31x performance degradation compared with the conventional design. We succeed in implementing a very large merge sorter tree with 4,096 input leaves which cannot be implemented using the conventional design. This tree achieves a merging throughput of 149 million 64-bit elements per second while using 1.72% of slices and 7.48% of Block RAMs of the FPGA.","PeriodicalId":322499,"journal":{"name":"2016 Fourth International Symposium on Computing and Networking (CANDAR)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125404840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fork Bomb Attack Mitigation by Process Resource Quarantine","authors":"Gaku Nakagawa, S. Oikawa","doi":"10.1109/CANDAR.2016.0124","DOIUrl":"https://doi.org/10.1109/CANDAR.2016.0124","url":null,"abstract":"A fork bomb attack is a denial of service attack. An attacker generates many processes rapidly, exhausting the resources of the target computer systems. There are several previous work to detect and remove the processes that cause fork bomb attacks. However, the operating system with the previous methods have the risks to terminate inappropriate processes that do not fork bomb processes. In this paper, we propose a new method that named process resource quarantine. With the proposed method, the operating systems don't terminate the detected fork bomb processes. Instead of the termination, the operating systems make resource limitations for the detected processes and inspect them periodically. We implemented the proposed method on Linux kernel and executed several evaluation experiments. The results show that the proposed method is effective for fork bomb attacks mitigation.","PeriodicalId":322499,"journal":{"name":"2016 Fourth International Symposium on Computing and Networking (CANDAR)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123077150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Concurrency Control in Hardware Transactional Memory Considering Execution Path Variation","authors":"Anju Hirota, Keisuke Mashita, Tomoaki Tsumura","doi":"10.1109/CANDAR.2016.0026","DOIUrl":"https://doi.org/10.1109/CANDAR.2016.0026","url":null,"abstract":"Lock-based thread synchronization techniques have been commonly used in parallel programming on multi-core processors. However, lock can cause deadlocks and poor scalabilites, and Transactional Memory (TM) has been proposed and studied for lock-free synchronization. On TMs, transactions are executed speculatively in parallel as long as they do not encounter any conflicts on shared variables. On general HTMs, hardware implementations of TM, conflicts can degrade the performance of HTM because of the overhead for re-execution of transactions. To address this problem, various transaction scheduling algorithms for avoiding conflicts have been proposed. However in the existing algorithms, execution path variation is not considered at all. Some transactions have branch instructions, and they cause execution path variations of transaction, resulting in poor efficacy of the scheduling algorithms. In this paper, we propose a novel concurrency control based on the execution time of transactions with considering execution path variation. The result of the experiment shows that the execution time of HTM is reduced 61.6% at a maximum, and 13.8% on average with 16 threads.","PeriodicalId":322499,"journal":{"name":"2016 Fourth International Symposium on Computing and Networking (CANDAR)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133948492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Prediction of Future Loads Using Neural Networks for Energy-Efficient Computing","authors":"Jörg Lenhardt, W. Schiffmann, Stefan Jannevers","doi":"10.1109/CANDAR.2016.0105","DOIUrl":"https://doi.org/10.1109/CANDAR.2016.0105","url":null,"abstract":"In modern data centers a large amount of energy can be saved by intelligently distributing load on the available servers and transferring idle nodes into low energy modes. Distributing load leads to a more energy-efficient usage of the servers within a server farm. Additionally, the use of energy saving modes like suspend to main memory can decrease the energy consumption dramatically. The selection of nodes to be transferred into a low energy mode is based on the information of an energy-efficient load distribution. The usage of low energy modes requires knowledge about future loads. Having a variable load profile, i.e. variations in loads over time, leads to time periods in which servers are idle (denoted as gaps). Within these gaps, servers can be transferred into one of various supported energy saving modes. It is crucial to have information about future gaps in advance to make the right decision in regard to the chosen energy saving mode. Usually, information about the future is not directly available but can be predicted using sophisticated algorithms. In this paper, we present an approach to predict future loads using trends, seasonal data, and neural networks.","PeriodicalId":322499,"journal":{"name":"2016 Fourth International Symposium on Computing and Networking (CANDAR)","volume":"481 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132687168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Initial Study of Reconfigurable Neural Network Accelerators","authors":"Momoka Ohba, S. Shindo, Shinobu Miwa, Tomoaki Tsumura, Hayato Yamaki, H. Honda","doi":"10.1109/CANDAR.2016.0128","DOIUrl":"https://doi.org/10.1109/CANDAR.2016.0128","url":null,"abstract":"Neural networks or NNs are widely used for many machine learning applications such as image processing and speech recognition. Since general-purpose processors such as CPUs and GPUs are energy inefficient for computing NNs, application-specific hardware accelerators for NNs (a.k.a. neural network accelerators or NNAs) have been proposed to improve the energy efficiency. However, existing NNAs are too customized for computing specific NNs, and do not allow to change NN models or learning algorithms. This limitation prevents machine-learning researchers from exploiting NNAs, so we are developing a general-purpose NNA that has the capability to compute any NN. Our NNA equips with reconfigurable logic in addition to various custom logics, which is called reconfigurable NNA or RNNA. RNNA is highly tuned for the NN computation but allows end users to customize the hardware to compute their desired NN. This paper introduces the RNNA architecture, and reports the performance analysis of RNNA with a cycle-level simulator.","PeriodicalId":322499,"journal":{"name":"2016 Fourth International Symposium on Computing and Networking (CANDAR)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129059229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Minimax Approach for Access-Point Setup Optimization Using Throughput Measurements in IEEE802.11n Wireless Networks","authors":"K. Lwin, N. Funabiki, Khin Khin Zaw, Md. Selim Al Mamun, M. Kuribayashi","doi":"10.1109/CANDAR.2016.0062","DOIUrl":"https://doi.org/10.1109/CANDAR.2016.0062","url":null,"abstract":"Recently, an IEEE802.11n access point (AP) has become common in the wireless local-area network (WLAN) due to the high-speed data transmission using the multiple input multiple output (MIMO) technology. However, the signal propagation from the 802.11n AP may not be uniform in the circumferential direction because of multiple antennas in MIMO, in addition to the height direction. As a result, the data transmission speed between the AP and a host can be significantly affected by their relative setup conditions. In this paper, we propose a minimax approach for optimizing the 802.11n AP setup condition in terms of the height and the angles in an indoor environment using throughput measurements. First, we detect a bottleneck host that receives the weakest signal from the AP in the field using the throughput estimation model. Then, we optimize the AP setup by changing the height and directions while measuring throughputs. For evaluations, we confirm the accuracy of the model using measurement results and the throughput improvements at most hosts including the bottleneck one in the field by our approach.","PeriodicalId":322499,"journal":{"name":"2016 Fourth International Symposium on Computing and Networking (CANDAR)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123600037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}