A Rapid Verification Framework for Developing Multi-core Processor

A multi-core processor is widely used to achieve both high performance and low energy consumption. However, verification of a multi-core processor is more difficult than that of single-core processor. Because multi-core processor has large and complex circuits, and special mechanisms such as a cache coherency mechanism also increases complexity. In general, design flow of a processor include such as the following steps; functional verification by high level language, cycle accurate verification by RTL simulation and timing analysis considered gate delay, wiring delay and others. In particular, co-simulation framework for single-core processor has been proposed to reduce time of cycle accurate verification with RTL simulation. However, if the conventional framework is applied to verify a multi-core processor, it causes three problems; failure of the co-simulation framework by a mismatch of load and store operation, failure of the system call emulation by cache coherency mechanism and requirement of task scheduling by execution multi-threaded program. These problems makes verification of a multi-core processor difficult seriously and increases simulation time dramatically. Therefore, this paper proposes a rapid verification framework to support execution of a multi-threaded program for multi-core processors. The proposed method makes it possible to verify both a homogeneous and heterogeneous multi-core processors with the cache coherency mechanism, and to execute multithreaded programs without full system simulation. The proposed framework extends conventional co-simulation framework for a single-core processor. The proposed framework is composed of the following three extensions; bypassing loaded value from the verified processor to virtual processor, a cache access mechanism for system call emulation, and an internal task scheduler. As evaluation results, our framework verifies two-core processor correctly. Furthermore, the proposed method achieves to reduce the number of execution cycles by 71% in maximum and 46% in average compared with full system simulation.