2016 Fourth International Symposium on Computing and Networking (CANDAR)最新文献_第6页

A Hardware Sorter for Almost Sorted Sequences, with FPGA Implementations 几乎排序序列的硬件排序器，带FPGA实现

2016 Fourth International Symposium on Computing and Networking (CANDAR) Pub Date : 2016-11-01 DOI: 10.1109/CANDAR.2016.0103

N. Harada, N. Matsumoto, K. Nakano, Yasuaki Ito

引用次数: 2

Process Mining Meets Malware Evolution: A Study of the Behavior of Malicious Code 过程挖掘与恶意软件演化:恶意代码行为的研究

2016 Fourth International Symposium on Computing and Networking (CANDAR) Pub Date : 2016-11-01 DOI: 10.1109/CANDAR.2016.0111

M. Bernardi, Marta Cimitile, F. Mercaldo

{"title":"Process Mining Meets Malware Evolution: A Study of the Behavior of Malicious Code","authors":"M. Bernardi, Marta Cimitile, F. Mercaldo","doi":"10.1109/CANDAR.2016.0111","DOIUrl":"https://doi.org/10.1109/CANDAR.2016.0111","url":null,"abstract":"Mobile phones are more and more used for sensitive resources exchange and access, becoming target for possible malware attacks. These attacks are still increasing with the birth of new and sophisticated malware that make the existing malware detection approaches often inadequate. Since the majority of new malware are generated using existing malicious code, it becomes very important tracking the mobile malware phylogeny. In this work, a Process Mining (PM) approach for building a malware phylogeny model using information contained in system calls traces, is proposed. The adoption of a declarative Process Mining technique allows to mine a constraint-based model that can be effectively used as a malware fingerprint expressing relationships and recurring execution patterns among system calls in the execution flows. The model characterizes the behavior of malware applications allowing the identification of similarities across malware families and among malware variants belonging to the same family. The proposed approach is evaluated using a dataset of more than 700 infected applications across seven malware families obtaining very encouraging results.","PeriodicalId":322499,"journal":{"name":"2016 Fourth International Symposium on Computing and Networking (CANDAR)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124716913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

On Limiting Measures for a Class of One-Dimensional Linear Cellular Automata 一类一维线性元胞自动机的极限测度

2016 Fourth International Symposium on Computing and Networking (CANDAR) Pub Date : 2016-11-01 DOI: 10.1109/CANDAR.2016.0049

Masato Takei

{"title":"On Limiting Measures for a Class of One-Dimensional Linear Cellular Automata","authors":"Masato Takei","doi":"10.1109/CANDAR.2016.0049","DOIUrl":"https://doi.org/10.1109/CANDAR.2016.0049","url":null,"abstract":"Linear cellular automata have many invariant measures in general, but the most natural one is the uniform Bernoulli product measure. There are several studies on their rigidity: The unique invariant measure with a suitable non-degeneracy condition (such as positive entropy or mixing property for the shift map) is the uniform measure. This is related to study of the asymptotic randomization property: Iterates starting from a large class of initial measures converge to the uniform measure (in Cesaro sense). In this paper we consider one-dimensional linear cellular automata with neighborhood of size two, and study limiting distributions starting from a class of shift-invariant probability measures. We characterize when iterates by addition modulo a prime number cellular automata starting from a strong mixing probability measure with full support can converge. This also gives all invariant measures inside the class of those probability measures. In the two-state case, we also obtain a necessary and sufficient condition that a convex combination of strong mixing probability measures is invariant under addition modulo 2 cellular automata. Those results improve previous ones obtained by Marcovici and Miyamoto.","PeriodicalId":322499,"journal":{"name":"2016 Fourth International Symposium on Computing and Networking (CANDAR)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127165864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Feasibility Study for Building Hybrid Storage System Consisting of Non-volatile DIMM and SSD 构建非易失性DIMM与SSD混合存储系统的可行性研究

2016 Fourth International Symposium on Computing and Networking (CANDAR) Pub Date : 2016-11-01 DOI: 10.1109/CANDAR.2016.0085

Kazuichi Oe, T. Nanri, K. Okamura

{"title":"Feasibility Study for Building Hybrid Storage System Consisting of Non-volatile DIMM and SSD","authors":"Kazuichi Oe, T. Nanri, K. Okamura","doi":"10.1109/CANDAR.2016.0085","DOIUrl":"https://doi.org/10.1109/CANDAR.2016.0085","url":null,"abstract":"Various vendors develop a byte accessible Nonvolatile Dual-Inline Memory Module (NVDIMM). The performance of the NVDIMM drastically surpasses that of the Solid State Drive (SSD), which is connected by PCI express. However, the cost of the NVDIMM is much higher than that of the SSD. Therefore, a hybrid storage system between the NVDIMM and SSD is an effective technique for improving cost-performance. If a system uses the NVDIMM less while maintaining performance, its cost-performance should be improved. Our previous work involves on-the-fly automated storage tiering (OTF-AST). OTF-AST is a hybrid storage system consisting of an SSD and HDD. It aims to reduce the average response time of IO accesses by migrating only the IO concentration area to the SSD when IO concentration happens. Therefore, we construct OTF-AST with both the DIMM and SSD and evaluate it in order to understand how to build a cost-effective hybrid storage system with these devices. We use a DIMM instead of a byte accessible NVDIMM, which is difficult to obtain. As a result, we found that the original OTF-AST is suitable for a hybrid storage system consisting of the DIMM and SSD. Moreover, we can improve the performance of OTF-AST if replace its migration algorithm with a more positive migration algorithm. This is because the IO access response time barely increases when the data migration between the DIMM and SSD is done. We will build a more positive migration algorithm in the near future.","PeriodicalId":322499,"journal":{"name":"2016 Fourth International Symposium on Computing and Networking (CANDAR)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128911937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Energy Efficient Processing of Fine-Grained Loads in Heterogeneous Server Farms 异构服务器群中细粒度负载的节能处理

2016 Fourth International Symposium on Computing and Networking (CANDAR) Pub Date : 2016-11-01 DOI: 10.1109/CANDAR.2016.0030

Jörg Lenhardt, W. Schiffmann

引用次数: 1

PGASUS: A Framework for C++ Application Development on NUMA Architectures PGASUS:一个基于NUMA架构的c++应用程序开发框架

2016 Fourth International Symposium on Computing and Networking (CANDAR) Pub Date : 2016-11-01 DOI: 10.1109/CANDAR.2016.0071

W. Hagen, Max Plauth, Felix Eberhardt, Frank Feinbube, A. Polze

{"title":"PGASUS: A Framework for C++ Application Development on NUMA Architectures","authors":"W. Hagen, Max Plauth, Felix Eberhardt, Frank Feinbube, A. Polze","doi":"10.1109/CANDAR.2016.0071","DOIUrl":"https://doi.org/10.1109/CANDAR.2016.0071","url":null,"abstract":"For the implementation of data-intensive C++ applications for cache coherent Non-Uniform Memory Access (NUMA) systems, both massive parallelism and data locality have to be considered. While massive parallelism has been largely understood, the shared memory paradigm is still deeply entrenched in the mindset of many C++ software developers. Hence, data locality aspects of NUMA systems have been widely neglected thus far. At first sight, applying shared nothing approaches might seem like a viable workaround to address locality. However, we argue that developers should be enabled to address locality without having to surrender the advantages of the shared address space of cache coherent NUMA systems. Based on an extensive review of parallel programming languages and frameworks, we propose a programming model specialized for NUMA-aware C++ development that incorporates essential mechanisms for parallelism and data locality. We suggest that these mechanisms should be used to implement specialized data structures and algorithm templates which encapsulate locality, data distribution, and implicit data parallelism. We present an implementation of the proposed programming model in the form of a C++ framework. To demonstrate the applicability of our programming model, we implement a prototypical application on top of this framework and evaluate its performance.","PeriodicalId":322499,"journal":{"name":"2016 Fourth International Symposium on Computing and Networking (CANDAR)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124567604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Performance Comparison of CGRA and Mobile GPU for Light-Field Image Processing CGRA与移动GPU光场图像处理性能比较

2016 Fourth International Symposium on Computing and Networking (CANDAR) Pub Date : 2016-11-01 DOI: 10.1109/CANDAR.2016.0040

Yuttakon Yuttakonkit, Y. Nakashima

{"title":"Performance Comparison of CGRA and Mobile GPU for Light-Field Image Processing","authors":"Yuttakon Yuttakonkit, Y. Nakashima","doi":"10.1109/CANDAR.2016.0040","DOIUrl":"https://doi.org/10.1109/CANDAR.2016.0040","url":null,"abstract":"Recently, many approaches apply light-field image processing on smartphones and wearable devices. A Graphic Processing Unit (GPU) is commonly used to exploit parallelism in such image processing. However, because the access pattern in the light-field application is more sparse than typical stencil applications and does not use all data in a cache line. Furthermore, the data requests to multiple locations generate enormous short-burst memory transfers in the cache system, cost high latency, and do not fully utilize the high memory bandwidth of GPU. Therefore, an alternative architecture that exploits a long-burst data transmission, which improves the memory bandwidth utilization, is essential. We propose a sparse stencil oriented Coarse Grain Reconfigurable Accelerator (CGRA) that we call EMAXV. Unlike on-demand multiple data loading on GPU, EMAXV loads the input data with a long burst transferring before the execution proceeds to conceal the sparse memory access and multi-threading cache races. It further obscures the memory loading latency with an execution latency from different activations. We evaluated the EMAXV and mobile GPU (Tegra K1) performances with identical host CPU's frequency and main memory bandwidth. Although EMAXV has much lower computation capability, we achieved four times performance of mobile GPU for light-field depth extraction and 89% of the performance for light-field image rendering.","PeriodicalId":322499,"journal":{"name":"2016 Fourth International Symposium on Computing and Networking (CANDAR)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121421210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

On Sensor Fusion for Location-Based Recommender Systems 基于位置的推荐系统传感器融合研究

2016 Fourth International Symposium on Computing and Networking (CANDAR) Pub Date : 2016-11-01 DOI: 10.1109/CANDAR.2016.0055

J. Dunkel

引用次数: 0

An Evaluation of the Parallella Architecture for the Convex Hull Computation 凸包计算中平行结构的评价

2016 Fourth International Symposium on Computing and Networking (CANDAR) Pub Date : 2016-11-01 DOI: 10.1109/CANDAR.2016.0127

K. Nakata, Yasuaki Ito

引用次数: 0

CPU Meets VR: A Scalable 3D Representation of Manycores for Behavior Analysis CPU满足VR:多核行为分析的可扩展3D表示

2016 Fourth International Symposium on Computing and Networking (CANDAR) Pub Date : 2016-11-01 DOI: 10.1109/CANDAR.2016.0072

Hiromasa Kato, S. Shimaya, Keisuke Fujimoto, Tomoya Kameda, T. Tran, Shinya Takamaeda-Yamazaki, Y. Nakashima

{"title":"CPU Meets VR: A Scalable 3D Representation of Manycores for Behavior Analysis","authors":"Hiromasa Kato, S. Shimaya, Keisuke Fujimoto, Tomoya Kameda, T. Tran, Shinya Takamaeda-Yamazaki, Y. Nakashima","doi":"10.1109/CANDAR.2016.0072","DOIUrl":"https://doi.org/10.1109/CANDAR.2016.0072","url":null,"abstract":"Modern microprocessors have a number of cores and complicated structures, such as multi-level caches. Behavior analysis of modern complicated processors is important for software performance optimizations, processor architecture researches, and education purposes. Currently, a number of tools are available for checking the behavior of processors such as processor simulators, debuggers and profilers. However, it takes effort to understand the contents because these tools provide only statistical information such as total count of cache misses. Therefore, in this paper, we propose a novel representation method of internal microprocessor behaviors by using a 3D VR (Virtual Reality) system. The proposed method is scalable to the number of cores on a processor. In order to represent in scalable and efficiently in 3D space, we investigated about the arrangement and shape of the graphics component, and abstract representation of the information. Also, we implemented a prototype system with the proposed method, on\"Unity\"gaming engine. Our system shows cache miss and number of Instructions Per Cycle (IPC) as the output results of a processor simulator. The evaluation result of the prototype system shows that the system is able to display a wide range of processor configurations on a limited 3D space with acceptable quality of 3D images. So that, our method is suitable for being utilized into the modern many-core processor architectures.","PeriodicalId":322499,"journal":{"name":"2016 Fourth International Symposium on Computing and Networking (CANDAR)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117091614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0