Hiromasa Kato, S. Shimaya, Keisuke Fujimoto, Tomoya Kameda, T. Tran, Shinya Takamaeda-Yamazaki, Y. Nakashima
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CPU Meets VR: A Scalable 3D Representation of Manycores for Behavior Analysis
Modern microprocessors have a number of cores and complicated structures, such as multi-level caches. Behavior analysis of modern complicated processors is important for software performance optimizations, processor architecture researches, and education purposes. Currently, a number of tools are available for checking the behavior of processors such as processor simulators, debuggers and profilers. However, it takes effort to understand the contents because these tools provide only statistical information such as total count of cache misses. Therefore, in this paper, we propose a novel representation method of internal microprocessor behaviors by using a 3D VR (Virtual Reality) system. The proposed method is scalable to the number of cores on a processor. In order to represent in scalable and efficiently in 3D space, we investigated about the arrangement and shape of the graphics component, and abstract representation of the information. Also, we implemented a prototype system with the proposed method, on"Unity"gaming engine. Our system shows cache miss and number of Instructions Per Cycle (IPC) as the output results of a processor simulator. The evaluation result of the prototype system shows that the system is able to display a wide range of processor configurations on a limited 3D space with acceptable quality of 3D images. So that, our method is suitable for being utilized into the modern many-core processor architectures.