CPU满足VR:多核行为分析的可扩展3D表示

Hiromasa Kato, S. Shimaya, Keisuke Fujimoto, Tomoya Kameda, T. Tran, Shinya Takamaeda-Yamazaki, Y. Nakashima
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引用次数: 0

摘要

现代微处理器有许多核心和复杂的结构,比如多级缓存。现代复杂处理器的行为分析对于软件性能优化、处理器体系结构研究和教学具有重要意义。目前,有许多工具可用于检查处理器的行为,例如处理器模拟器、调试器和分析器。但是,要理解内容需要花费一些精力,因为这些工具只提供统计信息,例如缓存丢失总数。因此,在本文中,我们提出了一种利用3D VR(虚拟现实)系统来表示微处理器内部行为的新方法。该方法可根据处理器的核数进行扩展。为了在三维空间中进行可扩展和高效的表示,我们研究了图形组件的排列和形状,以及信息的抽象表示。此外,我们在“Unity”游戏引擎上使用所提出的方法执行了一个原型系统。我们的系统显示缓存丢失和每周期指令数(IPC)作为处理器模拟器的输出结果。原型系统的评估结果表明,该系统能够在有限的三维空间内显示多种处理器配置,并具有可接受的三维图像质量。因此,我们的方法适用于现代多核处理器体系结构。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
CPU Meets VR: A Scalable 3D Representation of Manycores for Behavior Analysis
Modern microprocessors have a number of cores and complicated structures, such as multi-level caches. Behavior analysis of modern complicated processors is important for software performance optimizations, processor architecture researches, and education purposes. Currently, a number of tools are available for checking the behavior of processors such as processor simulators, debuggers and profilers. However, it takes effort to understand the contents because these tools provide only statistical information such as total count of cache misses. Therefore, in this paper, we propose a novel representation method of internal microprocessor behaviors by using a 3D VR (Virtual Reality) system. The proposed method is scalable to the number of cores on a processor. In order to represent in scalable and efficiently in 3D space, we investigated about the arrangement and shape of the graphics component, and abstract representation of the information. Also, we implemented a prototype system with the proposed method, on"Unity"gaming engine. Our system shows cache miss and number of Instructions Per Cycle (IPC) as the output results of a processor simulator. The evaluation result of the prototype system shows that the system is able to display a wide range of processor configurations on a limited 3D space with acceptable quality of 3D images. So that, our method is suitable for being utilized into the modern many-core processor architectures.
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