几乎排序序列的硬件排序器，带FPGA实现

2016 Fourth International Symposium on Computing and Networking (CANDAR) Pub Date : 2016-11-01 DOI:10.1109/CANDAR.2016.0103

N. Harada, N. Matsumoto, K. Nakano, Yasuaki Ito

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引用次数: 2

摘要

假设以异步方式传输带有时间戳的传感数据序列。一些传感数据可能会延迟一段时间，并且序列不符合时间戳的适当递增顺序。时间戳序列to, t1，…n- 1是d排序的，如果是

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A Hardware Sorter for Almost Sorted Sequences, with FPGA Implementations

Suppose that a sequence of sensing data with timestamps are transferred asynchronously. Some of sensing data may be delayed by some period of time and the sequence is not in proper increasing order of timestamps. A sequence of timestamps to, t1,..., tn-l is d-sorted if ti

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来源期刊

2016 Fourth International Symposium on Computing and Networking (CANDAR)

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