{"title":"A hybrid Sentiment Classification method using Neural Network and Fuzzy Logic","authors":"Jaydeep Balkrishna Sathe, M. Mali","doi":"10.1109/ISCO.2017.7855960","DOIUrl":"https://doi.org/10.1109/ISCO.2017.7855960","url":null,"abstract":"Neural Network(NN) and fuzzy systems are suitable for determining the input-output relationships. NN contend with numeric and quantitative information whereas fuzzy systems can handle symbolic and qualitative information. Coupling of Neural Network and Fuzzy Logic results in an intelligent crossbreed system widely referred to as Neuro-fuzzy system (NFS) that exploits the most effective qualities of these two approaches expeditiously. The coupled system combines the human alike logical reasoning of fuzzy systems with the training and connectedness structure of neural network. In this paper, we propose a method for performing Sentiment Classification using an NN and fuzzy set theory. In this method input reviews are fuzzified by using Gaussian membership function and fuzzification matrix is build. This matrix is transposed and passed to Multilayer Perceptron Backpropagation Network(MLPBPN).","PeriodicalId":321113,"journal":{"name":"2017 11th International Conference on Intelligent Systems and Control (ISCO)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132398851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Comparative study of single Material gate and Dual Material gate Silicon-On-Insulator Junctionless Transistors","authors":"S. C. Wagaj, Y. Chavan","doi":"10.1109/ISCO.2017.7855997","DOIUrl":"https://doi.org/10.1109/ISCO.2017.7855997","url":null,"abstract":"A Dual material gate silicon on Insulator Junctionless Transistor (DMG SOI JLT) is proposed in this paper. It's characteristics is demonstrated & compared with a single Material gate Silicon On Insulator Junctionless Transistor (SMG SOI JLT) using EDA tools used for simulation. The result shows that the DMG-SOI JLT has current driving capability higher than the single Material gate silicon on Insulator junctionless Transistor. The potential distribution of DMG SOI JLT has an abrupt change the transition of two gates and enhances the electric field in the channel. The channel length decrease then DIBL and sub threshold slope variation is minimum in DMG SOI JLT compare to SMG SOI JLT. Transconductance of SMG SOI JLT is observed 0.25mS for channel length 20nm.","PeriodicalId":321113,"journal":{"name":"2017 11th International Conference on Intelligent Systems and Control (ISCO)","volume":"456 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125799479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design analysis and implementation of MPPT based controlling mechanism for improving the efficiency of solar Photovoltaic based operated system","authors":"K. Deepti, P. Srihari, Manjunadh Achari","doi":"10.1109/ISCO.2017.7855993","DOIUrl":"https://doi.org/10.1109/ISCO.2017.7855993","url":null,"abstract":"In recent years the attention towards utilization of renewable sources of energy has been increased drastically. Solar energy is one of the important renewable sources of energy since it is clean, pollution free and inexhaustible. Though the initial installation cost is high the maintenance cost is considerable less. The output Power of Photovoltaic array always changes with weather conditions i.e., solar irradiation and atmospheric temperature. The energy that is being absorbed by photovoltaic cells is not being completely utilized because of irradiance effects. Hence Maximum power point tracking techniques(MPPT) are employed in photovoltaic systems to utilize the energy that is absorbed. These techniques vary in many aspects as range of effectiveness, hardware, sensor required, and cost. This paper presents a comparison analysis of existing MPPT techniques and then an optimal controller is designed and implemented which has a better performance in achieving high efficiency. In designing the controller circuit the algorithm that has proved the best basing on simulation results has been adopted for designing the controller circuit. The entire simulation was carried out using Matlab simulink tool. The model includes accepting the input from the available source by considering a step variation in the input conditions, a physical to simulink converter circuit, a DC-DC converter circuit with designed parameters according to the load considered and a controller circuit. Other technique of improving efficiency that is by rotating the panel to track the energy under shaded and unshaded conditions has been implemented and the real time model is presented.","PeriodicalId":321113,"journal":{"name":"2017 11th International Conference on Intelligent Systems and Control (ISCO)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125816678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Sridevi, M. Sundarambal, K. Muralidharan, R. Josephine
{"title":"FPGA implementation of hand gesture recognition system using neural networks","authors":"K. Sridevi, M. Sundarambal, K. Muralidharan, R. Josephine","doi":"10.1109/ISCO.2017.7856017","DOIUrl":"https://doi.org/10.1109/ISCO.2017.7856017","url":null,"abstract":"Gesture recognition enables human to communicate with machine and interact naturally without any mechanical devices. The ultimate aim of gesture recognition system is to create a system which understands human gesture and use them to control various other devices. This research focuses on gesture recognition system with a radial basis function network. The radial basis function network is a 3 layer network and trained with a radial basis function algorithm to identify the classes. The complete system is implemented on a Field Programmable Gate Array with image processing unit. The system is design to identify 24 American sign-language hand signs and also real time hand gesture signs. This combination leads to maximum recognition rate. The proposed system is very small due to FPGA implementation which is highly suitable for control of equipments at home, by the handicapped people.","PeriodicalId":321113,"journal":{"name":"2017 11th International Conference on Intelligent Systems and Control (ISCO)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130331772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sudheesh P G, Chiranjeevi Manda, P. Muthuchidambaranathan
{"title":"On frequency domain Channel estimation using WARP v3 hardware platform","authors":"Sudheesh P G, Chiranjeevi Manda, P. Muthuchidambaranathan","doi":"10.1109/ISCO.2017.7855994","DOIUrl":"https://doi.org/10.1109/ISCO.2017.7855994","url":null,"abstract":"Multi antenna wireless systems, which is generally termed as multi-input multi-output (MIMO) systems offers greater channel capacity and reliability compared to the single-input single-output (SISO) systems. It is important for the system to know the channel state information (CSI) for exploiting better performance of the communication system. The instantaneous CSI is acquired in an indoor scenario using the hardware setup. In this paper we use WARP v3 kit to extract the CSI with Orthogonal frequency division multiplexing (OFDM) and without OFDM.","PeriodicalId":321113,"journal":{"name":"2017 11th International Conference on Intelligent Systems and Control (ISCO)","volume":"246 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115283823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Anti-collision algorithm for RFID system using adaptive Bayesian Belief Networks and it's VLSI Implementation","authors":"J. Bag, Subhashis Roy, S. Sarkar","doi":"10.1109/ISCO.2017.7856007","DOIUrl":"https://doi.org/10.1109/ISCO.2017.7856007","url":null,"abstract":"In Radio Frequency Identification system, reader collision problems are generally mitigated by maximizing the total effective interrogation area of an RFID reader network or by automatic adjustable frame size of reader, etc. This paper proposes a novel anti-collision algorithm for RFID system using adaptive Bayesian Belief Networks. Bayesian belief networks are suitable for target recognition within a network using the category, identity and type or class of a target. These three attributes are being modelled based on the theory, which relies on previous and related trials approach. It is a classical problem which uses the observers' belief that an event will occur or not. Similarly, it can predict from previous trial reports whether a node is reliable or not. An RFID network faced with the reader collision problem when multiple readers are deployed densely and enters the region of another reader. Tags receive signal from more than one reader and instant identification by a single reader becomes a problem. The aim of this paper is to develop an efficient anti-collision algorithm, where using BBN, the reader identifies foreign elements like unwanted tags and readers and detect the specific/authentic tags. Similarly, the tag can respond the specific reader only and rejecting signal from unwanted readers, thus control the transmitting characteristics and minimizes the collision problems. In this paper, the authenticity checker is developed and implemented for RFID system using VHDL code and simulated the design with Xilinx ISE 14.3 simulation tools and high performance FPGA board.","PeriodicalId":321113,"journal":{"name":"2017 11th International Conference on Intelligent Systems and Control (ISCO)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131139947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A randomization based computation of RSA to resist power analysis attacks","authors":"H. J. Mahanta, Sibbir Ahmed, Ajoy Kumar Khan","doi":"10.1109/ISCO.2017.7856010","DOIUrl":"https://doi.org/10.1109/ISCO.2017.7856010","url":null,"abstract":"This paper presents an overview on the randomization technique. Randomization has been considered as one of the efficient techniques to resist power analysis attack on exponentiation based cryptographic algorithm. RSA is one of the most widely used public key cryptosystem. It uses exponentiation operation for encryption / decryption of data. If the instantaneous power consumed during the exponential operation is monitored, it could reveal the operation as well as secret data. Here we have proposed a randomization based exponentiation calculation method that could resist power analysis attacks on RSA.","PeriodicalId":321113,"journal":{"name":"2017 11th International Conference on Intelligent Systems and Control (ISCO)","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116913625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optimal design of reversible parity preserving new Full adder / Full subtractor","authors":"P.Kiran Kumar, P. Rao, K. Kishore","doi":"10.1109/ISCO.2017.7856019","DOIUrl":"https://doi.org/10.1109/ISCO.2017.7856019","url":null,"abstract":"The widely using CMOS technology implementing with irreversible logic will hit a scaling limit beyond 2020 and the major limiting factor is increased power dissipation. The irreversible logic is replaced by reversible logic to decrease the power dissipation. The devices implemented with reversible logic gates will have demand for the upcoming future computing technologies as they consumes less power. Reversible logic has applications in Low Power VLSI, Quantum Computing, Nanotechnology and Optical computing. This paper proposes the design of a optimal fault tolerant Full adder / Full subtractor. For this logic circuit input parity and output parity is same hence it is called parity preserving circuit. The proposed method require less complexity, less hardware, minimum number of gates, minimum number of garbage inputs and minimum number of constant inputs than existing methods.","PeriodicalId":321113,"journal":{"name":"2017 11th International Conference on Intelligent Systems and Control (ISCO)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128864197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A comparative study of transform domain methods for image resolution enhancement of satellite image","authors":"M. Rathod, Jayshree Khanapuri","doi":"10.1109/ISCO.2017.7856000","DOIUrl":"https://doi.org/10.1109/ISCO.2017.7856000","url":null,"abstract":"Satellite images are being used in various fields of research over the years. One of the major limitations of some of these images is their resolution. Therefore, image resolution enhancement is the first necessary step in image processing. Image resolution enhancement is the process of modifying the images under consideration so that obtained image is more appropriate than the original image for required application. Image resolution is important aspect of any image. Good quality image i.e. high-resolution image produces better results in image processing application. Resolution enhancement can be done in various domains such as spatial & transform domains. Different transform domain methods that are used for image resolution enhancement are namely, Discrete Wavelet transform (DWT), Stationary Wavelet Transform (SWT), Discrete Cosine Transform (DCT), Dual-Tree Complex Wavelet Transform (DT-CWT) etc. Out of these, DT-CWT is found to be one of the most effective methods. In this paper, we have analyzed different approaches based on interpolation for image resolution enhancement. The discussion and comparison of different transform domain methods for image resolution enhancement is carried out on satellite benchmark images and analytical results showing the supremacy among these methods for image resolution enhancement is presented.","PeriodicalId":321113,"journal":{"name":"2017 11th International Conference on Intelligent Systems and Control (ISCO)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121049907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Raja, S. Saravanan, P. Malini, V. Raveena, Ravipati Praveena
{"title":"Design of a spike detector for fully Integrated Neuromodulation SoC","authors":"K. Raja, S. Saravanan, P. Malini, V. Raveena, Ravipati Praveena","doi":"10.1109/ISCO.2017.7856013","DOIUrl":"https://doi.org/10.1109/ISCO.2017.7856013","url":null,"abstract":"The paper presents a new spike detector proposed for the Neuromodulation SoC. The SoC designed combines the 64 acquisition channels with digital compression and simulation. The objective of this work is to design a spike detector for event detector. In literature several designs available which uses above 90nm technology with supply voltage greater than 1.8V. The spike detector consists of an non linear energy operator, moving average filter, pipeline stage, processing elements like multiplier, adder and comparator. The design supports adaptive thersholding for event detector which depends on the physiological parameters like electrode movements, skin impedance, etc. This work proposes a design in 65nm and 45nm, the system works in supply voltage less than 1V by which the power consumption is reduced. The lower technology allows the design to be area efficient.","PeriodicalId":321113,"journal":{"name":"2017 11th International Conference on Intelligent Systems and Control (ISCO)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122143507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}