Optimal design of reversible parity preserving new Full adder / Full subtractor

Abstract

The widely using CMOS technology implementing with irreversible logic will hit a scaling limit beyond 2020 and the major limiting factor is increased power dissipation. The irreversible logic is replaced by reversible logic to decrease the power dissipation. The devices implemented with reversible logic gates will have demand for the upcoming future computing technologies as they consumes less power. Reversible logic has applications in Low Power VLSI, Quantum Computing, Nanotechnology and Optical computing. This paper proposes the design of a optimal fault tolerant Full adder / Full subtractor. For this logic circuit input parity and output parity is same hence it is called parity preserving circuit. The proposed method require less complexity, less hardware, minimum number of gates, minimum number of garbage inputs and minimum number of constant inputs than existing methods.