Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.最新文献_第4页

A 2.5-Gb/s CMOS Clock And Data Recovery Circuit With A 1/4 Rate Linear Phase Detector And Lock Detector 带有1/4速率线性鉴相器和锁相器的2.5 gb /s CMOS时钟和数据恢复电路

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Pub Date : 2006-06-22 DOI: 10.1109/MIXDES.2006.1706562

S. Alavi, O. Shoaei

引用次数: 0

Optimization Of Geometric Parameters Of Spiral Inductors Using Genetic Algorithms 基于遗传算法的螺旋电感器几何参数优化

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Pub Date : 2006-06-22 DOI: 10.1109/MIXDES.2006.1706634

E. Gadjeva, V. Durev, M. Hristov, D. Pukneva

引用次数: 4

A SiGe Power Amplifier With Power Detector And VSWR Protection For TD-SCDMA Application 一种用于TD-SCDMA的带功率检测器和驻波保护的SiGe功率放大器

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Pub Date : 2006-06-22 DOI: 10.1109/MIXDES.2006.1706571

Q. Hu, Z.H. Liu, L. Yan, W. Zhou

引用次数: 11

Study On pH-ISFET Temperature Effect Using Implemented MOS Transistor 利用实现的MOS晶体管研究pH-ISFET温度效应

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Pub Date : 2006-06-22 DOI: 10.1109/MIXDES.2006.1706636

I. Humenyuk, S. Palomar, D. Lagrange, S. Assié, B. Franck, P. Marcoul, D. Medale, A. Martinez, P. Temple-Boyer

引用次数: 1

Middle Surface Approximtaion For Parallel And Distributed Substrate Coupling Analysis 平行和分布衬底耦合分析的中间表面近似

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Pub Date : 2006-06-22 DOI: 10.1109/MIXDES.2006.1706627

M. A. Karami, N. Masoumi

引用次数: 1

Optimization Of Control Memory Size Of Control Unit With Codes Sharing 基于代码共享的控制单元控制内存大小优化

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Pub Date : 2006-06-22 DOI: 10.1109/MIXDES.2006.1706598

A. Barkalov, M. Kolopienczyk, L. Titarenko

引用次数: 8

A Measurement Technique To Obtain The Delay Time Of A Comparator In 120nm CMOS 一种获得120nm CMOS比较器延迟时间的测量技术

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Pub Date : 2006-06-22 DOI: 10.1109/MIXDES.2006.1706643

B. Goll, M. Spinola Durante, H. Zimmermann

{"title":"A Measurement Technique To Obtain The Delay Time Of A Comparator In 120nm CMOS","authors":"B. Goll, M. Spinola Durante, H. Zimmermann","doi":"10.1109/MIXDES.2006.1706643","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706643","url":null,"abstract":"The delay time of a regenerative comparator can be in the range of some tens of picoseconds. In this paper, an on-chip measurement technique is presented to obtain this delay time. For this task simple RC low-passes and different variants of implementing a fast XOR gate are examined to determine a short time difference, where after sampling the logic decision at the inverted and non-inverted output of the comparator, both outputs overlap with the same logical value. This time-difference is identified as the delay time of the comparator and occurs, if in the reset phase of the comparator the output nodes are pulled to the same logical value. An advantage of this technique is that only a DC voltage has to be measured outside the chip, which is proportional to the delay time and which is not influenced by bond wire inductances. A test-chip with the low-power comparator and a test-bed for delay-time detection was manufactured in a 120nm CMOS technology with a supply voltage of 1.5V. Compared with simulation results it turns out that a simple RC low-pass is sufficient for delay measurements. When applying a rectangular signal at the input of the implemented comparator, a minimal resolution of 8mV at a clock frequency of 1.5GHz was reached. The power consumption of the comparator was 160muW at 1.5GHz and the offset voltage was typically l0mV","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116422547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Si Circuits Design Automation Using Ample Language 用Ample语言设计Si电路自动化

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Pub Date : 2006-06-22 DOI: 10.1109/MIXDES.2006.1706604

P. Sniatala, R. Rudnicki

引用次数: 0

Lumped Element Behavioural High Voltage MOS Model 集总元件行为高压MOS模型

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Pub Date : 2006-06-22 DOI: 10.1109/MIXDES.2006.1706559

S. Schmidt, M. Franke

{"title":"Lumped Element Behavioural High Voltage MOS Model","authors":"S. Schmidt, M. Franke","doi":"10.1109/MIXDES.2006.1706559","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706559","url":null,"abstract":"High voltage MOS transistors usually have a drift zone in the drain region. The conductivity of this drift zone is strongly dependent on the flowing current and gate voltage. Thus it has generally to be modelled with a variable resistance representing the effects on the current. The goal of this work is to show a phenomenological macro model including AC modelling. The model is restricted to a lumped element sub-circuit, which can be processed by a standard Spice simulator. A drain resistance can be described by a behavioural source and a resistance in series. The source could be a current or voltage source controlled by drain current and gate voltage. The example discussed in this paper describes a sub-circuit containing a current source with a resistor in series as well as a model of the voltage dependent gate to drain capacitance. One of the most important goals of development was a fast convergence of the transient simulation. This was achieved by a restriction of the mathematical formula for the current function. The model is tested by means of a ring oscillator. The results have been satisfactory for DC, AC as well as transient analysis","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129130058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Noise-power Trade-off In CMOS-G/sub M/-C Channel Select Filters CMOS-G/sub / c通道选择滤波器的噪声-功率权衡

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Pub Date : 2006-06-22 DOI: 10.1109/MIXDES.2006.1706597

N. Christoffers, T. Fedtschenko, T. Stucke, R. Kokozinski, S. Kolnsberg

引用次数: 1