16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)最新文献_第5页

Fault diagnosis aware ATE assisted test response compaction 故障诊断感知ATE辅助测试响应压缩

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722302

J. M. Howard, S. Reddy, I. Pomeranz, B. Becker

引用次数: 2

The alarms project: A hardware/software approach to addressing parameter variations 警报项目:处理参数变化的硬件/软件方法

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722200

D. Brooks

{"title":"The alarms project: A hardware/software approach to addressing parameter variations","authors":"D. Brooks","doi":"10.1109/ASPDAC.2011.5722200","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722200","url":null,"abstract":"Parameter variations (process, voltage, and temperature) threaten continued performance scaling of power-constrained computer systems. As designers seek to contain the power consumption of microprocessors through reductions in supply voltage and power-saving techniques such as clock-gating, these systems suffer increasingly large power supply fluctuations due to the finite impedance of the power supply network. These supply fluctuations, referred to as voltage emergencies, must be managed to guarantee correctness. Traditional approaches to address this problem incur high-cost or compromise power/performance efficiency. Our research seeks ways to handle these alarm conditions through a combined hardware/software approach, motivated by root cause analysis of voltage emergencies revealing that many of these events are heavily linked to both program control flow and microarchitectural events (cache misses and pipeline flushes). This talk will discuss three aspects of the project: (1) a fail-safe mechanism that provides hardware guaranteed correctness; (2) a voltage emergency predictor that leverages control flow and microarchitectural event information to predict voltage emergencies up to 16 cycles in advance; and (3) a proof-of-concept dynamic compiler implementation that demonstrates that dynamic code transformations can be used to eliminate voltage emergencies from the instruction stream with minimal impact on performance [1–9].","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"119 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129328709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Facilitating unreachable code diagnosis and debugging 促进不可达代码的诊断和调试

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722238

Hong-Zu Chou, Kai-Hui Chang, S. Kuo

引用次数: 8

A fine-grained technique of NBTI-aware voltage scaling and body biasing for standard cell based designs 基于标准电池设计的nbti感知电压缩放和体偏置的细粒度技术

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722260

Yongho Lee, Taewhan Kim

{"title":"A fine-grained technique of NBTI-aware voltage scaling and body biasing for standard cell based designs","authors":"Yongho Lee, Taewhan Kim","doi":"10.1109/ASPDAC.2011.5722260","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722260","url":null,"abstract":"As the technology scales, the increase of circuit delay over time due to NBTI (negative bias temperature instability) effect is not negligible any more. It has been known that voltage scaling is an effective scheme that is able to mitigate the NBTI effect. However, a careful control of voltage scaling is required not to increase the dissipation of dynamic power significantly. On the other hand, body biasing can also be used to mitigate the NBTI effect by lowering down the threshold voltage, but its effectiveness is limited, as will be demonstrated in this work, and it increases the leakage power. This work addresses an important problem of minimizing the power consumption of circuit while controlling the NBTI induced delay increase to meet the circuit timing constraint by simultaneously utilizing the effects of voltage scaling and body biasing on both NBTI and power consumption. Precisely, we solve the problem of finding a set of supply and body biasing voltage values to apply circuit clusters on standard cell based design to minimize the total power consumption while satisfying the constraint of circuit life time, considering the NBTI induced delay factor in circuit timing computation. By a comprehensive analysis on the relations between the values of supply and body biasing voltages and the values of the resulting power consumption and NBTI induced delay, we precisely formulate the problem, and transform it into a problem of convex optimization to solve it efficiently. Through extensive experimentation using ISCAS benchmark designs, it is shown that the proposed approach to the simultaneous exploitation of supply voltage and body biasing is able to produce designs with 14% and 8% reduced energy consumption on average over the designs produced by the design time NBTI-aware guard-banding based voltage scaling [20] and the run time NBTI-aware voltage scaling [4], respectively.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117290396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 79

Device-parameter estimation with on-chip variation sensors considering random variability 考虑随机变异性的片上可变传感器的设备参数估计

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722274

Kenichi Shinkai, M. Hashimoto

引用次数: 6

Mathematical limits of parallel computation for embedded systems 嵌入式系统并行计算的数学极限

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722269

Jason Loew, J. Elwell, D. Ponomarev, P. Madden

引用次数: 0

Development of low power and high performance application processor (T6G) for multimedia mobile applications 为多媒体移动应用开发低功耗高性能应用处理器(T6G)

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722289

Y. Kitasho, Yu Kikuchi, T. Shimazawa, Y. Ohara, Masafumi Takahashi, Y. Masubuchi, Y. Oowaki

引用次数: 1

An enhanced leakage-aware scheduler for dynamically reconfigurable FPGAs 一种用于动态可重构fpga的增强泄漏感知调度器

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722270

Jen-Wei Hsieh, Yuan-Hao Chang, Wei-Li Lee

引用次数: 8

A robust ECO engine by resource-constraint-aware technology mapping and incremental routing optimization 基于资源约束感知技术映射和增量路径优化的鲁棒ECO引擎

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722218

Shao-Lun Huang, Chi-An Wu, Kai-Fu Tang, Chang-Hong Hsu, Chung-Yang Huang

引用次数: 14

Balanced truncation for time-delay systems via approximate Gramians 时滞系统的近似格拉姆式平衡截断

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722251

Xiang Wang, Qing Wang, Zheng Zhang, Quan Chen, N. Wong

引用次数: 21