An enhanced leakage-aware scheduler for dynamically reconfigurable FPGAs

Jen-Wei Hsieh, Yuan-Hao Chang, Wei-Li Lee
{"title":"An enhanced leakage-aware scheduler for dynamically reconfigurable FPGAs","authors":"Jen-Wei Hsieh, Yuan-Hao Chang, Wei-Li Lee","doi":"10.1109/ASPDAC.2011.5722270","DOIUrl":null,"url":null,"abstract":"The FPGAs (Field-Programmable Gate Array) are popular in hardware designs and even hardware/software co-designs. Due to the advance of manufacturing technologies, leakage power has become an important issue in the design of modern FPGAs. In particular, the partially dynamical reconfigurable FP-GAs allow the latency between FPGA reconfiguration and task execution for the performance consideration. However, this latency introduces unnecessary leakage power called leakage waste. In this work, we propose a leakage-aware scheduling algorithm to minimize the leakage waste without increasing the schedule length of tasks. In this algorithm, a priority dispatcher with a split-aware placement is proposed to reduce the scheduling complexity with considering the hardware constraints of FPGAs. A series of experiments based on synthetic designs demonstrates that the proposed algorithm could effectively reduce leakage waste with limited sacrifices on the task schedulability.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASPDAC.2011.5722270","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8

Abstract

The FPGAs (Field-Programmable Gate Array) are popular in hardware designs and even hardware/software co-designs. Due to the advance of manufacturing technologies, leakage power has become an important issue in the design of modern FPGAs. In particular, the partially dynamical reconfigurable FP-GAs allow the latency between FPGA reconfiguration and task execution for the performance consideration. However, this latency introduces unnecessary leakage power called leakage waste. In this work, we propose a leakage-aware scheduling algorithm to minimize the leakage waste without increasing the schedule length of tasks. In this algorithm, a priority dispatcher with a split-aware placement is proposed to reduce the scheduling complexity with considering the hardware constraints of FPGAs. A series of experiments based on synthetic designs demonstrates that the proposed algorithm could effectively reduce leakage waste with limited sacrifices on the task schedulability.
一种用于动态可重构fpga的增强泄漏感知调度器
fpga(现场可编程门阵列)在硬件设计甚至硬件/软件协同设计中都很流行。由于制造技术的进步,泄漏功率已成为现代fpga设计中的一个重要问题。特别是,出于性能考虑,部分动态可重构的FP-GAs允许FPGA重构和任务执行之间的延迟。然而,这种延迟引入了不必要的泄漏功率,称为泄漏浪费。在这项工作中,我们提出了一种泄漏感知调度算法,在不增加任务调度长度的情况下最大限度地减少泄漏浪费。该算法在考虑fpga硬件约束的情况下,提出了一种具有分块感知的优先级调度器,以降低调度复杂度。基于综合设计的一系列实验表明,该算法可以有效地减少泄漏浪费,同时对任务可调度性的影响有限。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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