16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)最新文献_第4页

Parallel cross-layer optimization of high-level synthesis and physical design 高级合成与物理设计的并行跨层优化

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722235

James Williamson, Yinghai Lu, L. Shang, H. Zhou, Xuan Zeng

{"title":"Parallel cross-layer optimization of high-level synthesis and physical design","authors":"James Williamson, Yinghai Lu, L. Shang, H. Zhou, Xuan Zeng","doi":"10.1109/ASPDAC.2011.5722235","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722235","url":null,"abstract":"Integrated circuit (IC) design automation has traditionally followed a hierarchical approach. Modern IC design flow is divided into sequentially-addressed design and optimization layers; each successively finer in design detail and data granularity while increasing in computational complexity. Eventual agreement across the design layers signals design closure. Obtaining design closure is a continual problem, as lack of awareness and interaction between layers often results in multiple design flow iterations. In this work, we propose parallel cross-layer optimization, in which the boundaries between design layers are broken, allowing for a more informed and efficient exploration of the design space. We leverage the heterogeneous parallel computational power in current and upcoming multi-core/many-core computation platforms to suite the heterogeneous characteristics of multiple design layers. Specifically, we unify the highlevel and physical synthesis design layers for parallel cross-layer IC design optimization. In addition, we introduce a massively-parallel GPU floorplanner with local and global convergence test as the proposed physical synthesis design layer. Our results show average performance gains of 11X speed-up over state-of-the-art.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130565881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Advanced system LSIs for home 3D system 用于家庭3D系统的高级系统lsi

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722287

Taka Suzuki

引用次数: 0

Template-based memory access engine for accelerators in SoCs 用于soc中加速器的基于模板的内存访问引擎

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722175

Bin Li, Zhen Fang, R. Iyer

引用次数: 6

A resilient on-chip router design through data path salvaging 通过数据路径抢救的弹性片上路由器设计

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722230

Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li

引用次数: 28

A provably good approximation algorithm for Rectangle Escape Problem with application to PCB routing 矩形逃逸问题的一种可证明的良好逼近算法，并应用于PCB布线

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.5555/1950815.1950974

Q. Ma, Hui Kong, Martin D. F. Wong, Evangeline F. Y. Young

引用次数: 16

FPGA prototyping using behavioral synthesis for improving video processing algorithm and FHD TV SoC design FPGA原型设计利用行为综合改进视频处理算法和FHD电视SoC设计

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722291

Masaru Takahashi

引用次数: 0

Energy/reliability trade-offs in fault-tolerant event-triggered distributed embedded systems 容错事件触发分布式嵌入式系统中的能量/可靠性权衡

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722283

Junhe Gan, F. Gruian, P. Pop, J. Madsen

引用次数: 14

All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter 全数字PMOS和NMOS过程可变性监视器利用缓冲环与脉冲计数器

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722297

Jaehyun Jeong, T. Iizuka, T. Nakura, M. Ikeda, K. Asada

引用次数: 3

Profile assisted online system-level performance and power estimation for dynamic reconfigurable embedded systems 动态可重构嵌入式系统的在线系统级性能和功率估计

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722285

Jingqing Mu, Roman L. Lysecky

引用次数: 3

Reconfiguration-aware real-time scheduling under QoS constraint QoS约束下的重构感知实时调度

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722174

H. Kooti, D. Mishra, E. Bozorgzadeh

{"title":"Reconfiguration-aware real-time scheduling under QoS constraint","authors":"H. Kooti, D. Mishra, E. Bozorgzadeh","doi":"10.1109/ASPDAC.2011.5722174","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722174","url":null,"abstract":"Due to the increase in demand for reconfigurability in embedded systems, schedulability in real-time task scheduling is challenged by non-negligible reconfiguration overheads. Reconfiguration of the system during task execution affects both deadline miss rate and deadline miss distribution. On the other hand, Quality of Service (QoS) in several embedded applications is not only determined by deadline miss rate but also the distribution of the tasks missing their deadlines (known as weakly-hard real-time systems). As a result, we propose to model QoS constraints as a set of constraints on dropout patterns (due to reconfiguration overhead) and present a novel online solution for the problem of reconfiguration-aware real-time scheduling. According to QoS constraints, we divide the ready instances of the tasks into two groups: critical and non-critical, then model each group as a network flow problem and provide an online scheduler for each group. We deployed our method on synthetic benchmarks as well as software defined radio implementation of VoIP on reconfigurable systems. Results show that our solution reduces the number of QoS violations by 19.01 times and 2.33 times (57.02%) in comparison with Bi-Modal Scheduler (BMS) [1] for synthetic benchmarks with low and high QoS constraint, respectively.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121157006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6