2023 24th International Symposium on Quality Electronic Design (ISQED)最新文献_第9页

Polynomial Formal Verification of a Processor: A RISC-V Case Study 处理器的多项式形式验证:一个RISC-V案例研究

2023 24th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2023-04-05 DOI: 10.1109/ISQED57927.2023.10129397

Lennart Weingarten, Alireza Mahzoon, Mehran Goli, R. Drechsler

{"title":"Polynomial Formal Verification of a Processor: A RISC-V Case Study","authors":"Lennart Weingarten, Alireza Mahzoon, Mehran Goli, R. Drechsler","doi":"10.1109/ISQED57927.2023.10129397","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129397","url":null,"abstract":"Formal verification is an important task to ensure the correctness of a circuit. In the last 30 years, several formal methods have been proposed to verify various architectures. However, the space and time complexities of these methods are usually unknown, particularly, when it comes to complex designs, e.g., processors. As a result, there is always unpredictability in the performance of the verification tool. If we prove that a formal method has polynomial space and time complexities, we can successfully resolve the unpredictability problem and ensure the scalability of the method.In this paper, we propose a Polynomial Formal Verification (PFV) method based on Binary Decision Diagrams (BDDs) to fully verify a RISC-V processor. We take advantage of partial simulation to extract the hardware related to each instruction. Then, we create the reference BDD for each instruction with respect to its size and function. Finally, we run a symbolic simulation for each hardware instruction and compare it with the reference model. We prove that the whole verification task can be carried out in polynomial space and time. The experiments demonstrate that the PFV of a RISC-V RV32I processor can be performed in less than one second.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114546068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

NetViz: A Tool for Netlist Security Visualization NetViz:一个网络列表安全可视化工具

2023 24th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2023-04-05 DOI: 10.1109/ISQED57927.2023.10129374

James Geist, Travis Meade, Shaojie Zhang, Yier Jin

引用次数: 0

Power Savings in USB Hubs Through A Proactive Scheduling Strategy 通过主动调度策略在USB集线器省电

2023 24th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2023-04-05 DOI: 10.1109/ISQED57927.2023.10129309

Bikrant Das Sharma, Abdul Rahman Ismail, Chris Meyers

引用次数: 0

H-Saber: An FPGA-Optimized Version for Designing Fast and Efficient Post-Quantum Cryptography Hardware Accelerators H-Saber:设计快速高效后量子加密硬件加速器的fpga优化版本

2023 24th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2023-04-05 DOI: 10.1109/ISQED57927.2023.10129356

Andrea Guerrieri, Gabriel Da Silva Marques, F. Regazzoni, A. Upegui

{"title":"H-Saber: An FPGA-Optimized Version for Designing Fast and Efficient Post-Quantum Cryptography Hardware Accelerators","authors":"Andrea Guerrieri, Gabriel Da Silva Marques, F. Regazzoni, A. Upegui","doi":"10.1109/ISQED57927.2023.10129356","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129356","url":null,"abstract":"With the performance promises of quantum computers, standard encryption algorithms can be defeated. For this reason, a set of new quantum-resistant algorithms have been proposed and submitted for a standardization contest initiated by NIST. While the submission requirement was ANSI C for the reference implementation, NIST encouraged providing software implementations optimized for different target platforms, such as high-performance CPUs, embedded microcontrollers, and FPGAs. Yet, none of the algorithms submitted any FPGA-optimized code, due to the large and expensive development time required for coding at RTL. High-Level synthesis (HLS) covers the gap by creating automatically hardware code for FPGA out of C/C++. However, the quality of results is suboptimal due to the limitation imposed by the inadequacy of source code for HLS. In this paper, we propose a version of Saber’s code optimized for FPGA targets. We show how we detected and improved the performance of the reference code, achieving competitive results compared to the hand-made RTL-based designs.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"68 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129879871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

On-Interposer Decoupling Capacitors Placement for Interposer-based 3DIC 基于中间体的3DIC的介子上去耦电容器放置

2023 24th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2023-04-05 DOI: 10.1109/ISQED57927.2023.10129288

Po-Yang Chen, Chang-Yun Liu, Hung-Ming Chen, Po-Tsang Huang

引用次数: 0

Self-Checking Performance Verification Methodology for Complex SoCs 复杂soc的自检性能验证方法

2023 24th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2023-04-05 DOI: 10.1109/ISQED57927.2023.10129396

P. Ghosh, V. N. D. Mai, Aditya Chopra, Baljinder Sood

{"title":"Self-Checking Performance Verification Methodology for Complex SoCs","authors":"P. Ghosh, V. N. D. Mai, Aditya Chopra, Baljinder Sood","doi":"10.1109/ISQED57927.2023.10129396","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129396","url":null,"abstract":"Modern SoCs are designed by integrating several IPs using various interconnect layers(NoC). Although the exact functionality of the device is of the highest importance, the correct behavior in terms of performance is a crucial factor. To gain a competitive edge in the market, safety-critical devices (such as automotive devices) must meet various performance-related requirements. In this paper, we propose a methodology that includes the automatic addition of expected performance numbers of each performance test in the testbench. The definition of two proposed performance metrics, developing a proposed performance scoreboard to implement a self-check mechanism in UVM testbench, and regression management of several hundred performance verification test cases run on SoC RTL. The proposed methodology has been applied to multiple commercial SoCs at the chip and sub-system levels and has detected several performance design flaws during the initial design phase. It has been improved the productivity of the design team also. In complicated SoCs, it has been proven helpful in the absence of any established standard technique for performance verification at the SoC level.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133076828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

HFGCN: High-speed and Fully-optimized GCN Accelerator HFGCN:高速、全优化的GCN加速器

2023 24th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2023-04-05 DOI: 10.1109/ISQED57927.2023.10129340

Mi-Sung Han, Jiwan Kim, Donggeon Kim, Hyunuk Jeong, Gilho Jung, Myeongwon Oh, Hyundong Lee, Yunjeong Go, Hyunwoo Kim, Jongbeom Kim, Taigon Song

引用次数: 0

ISSAC: An Self-organizing and Self-healing MAC Design for Intermittent Communication Systems 一种用于间歇通信系统的自组织自修复MAC设计

2023 24th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2023-04-05 DOI: 10.1109/ISQED57927.2023.10129347

Ruben Dominguez, Wen Zhang, Hongzhi Xu, Pablo Rangel, Chen Pan

{"title":"ISSAC: An Self-organizing and Self-healing MAC Design for Intermittent Communication Systems","authors":"Ruben Dominguez, Wen Zhang, Hongzhi Xu, Pablo Rangel, Chen Pan","doi":"10.1109/ISQED57927.2023.10129347","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129347","url":null,"abstract":"Recent advancements in Internet of Things (IoT) technology draws attention to Energy Harvesting (EH) systems as a promising energy-efficient solution to the limited sustainability in IoT edge devices. However, due to the weak and unstable nature of the ambient energy source, EH nodes are vulnerable to frequent power outages. Consequently, such outages will, unfortunately, reset the volatile time module onboard, which results in synchronization problems. To enable intermittent communication under energy harvesting scenarios with limited and unstable power supply, instead of merely minimizing the occurrence of a power outage, this work will also enable a smart and swift \"self-healing\" MAC protocol for desynchronized EH IoT devices to synchronize its timeline with the rest of the network for communication. To demonstrate the effectiveness, we will take the popular Long-range Wide Area Network (LoRaWAN) communication protocol as the backbone for upgrading, testing, and evaluation. The experiments conducted on LoRa Nodes demonstrate the effectiveness of the proposed techniques.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132644178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

AGRAS: Aging and memory request rate aware scheduler for PCM memories 用于PCM存储器的老化和内存请求率感知调度器

2023 24th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2023-04-05 DOI: 10.1109/ISQED57927.2023.10129369

N. Aswathy, H. Kapoor

{"title":"AGRAS: Aging and memory request rate aware scheduler for PCM memories","authors":"N. Aswathy, H. Kapoor","doi":"10.1109/ISQED57927.2023.10129369","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129369","url":null,"abstract":"Emerging non-volatile memories overcome the bottlenecks associated with traditional DRAM memories, such as low density and high energy. The high operating voltages required for such non-volatile memories make them vulnerable to Biased Temperature Instability (BTI) aging. The aging of a device can be controlled by the de-stress operation, where the stress voltage applied to the device is removed for a small duration. Performing de-stress in regular intervals helps to partially recover from age degradation. Such an interval-based de-stress can affect the service of regular requests and thus can hamper the system performance.To control the aging of PCM memories while maintaining the system performance, we propose AGRAS: age and memory request-rate aware scheduling method to schedule de-stress as well as regular requests. AGRAS schedules the de-stress operation only when the incoming request rate is not very high, thus controlling performance degradation. Additionally, it makes sure that in events of a prolonged high request rate, the de-stress gets scheduled in order to control device age degradation. The proposal helps to improve the system performance while minimizing the age degradation compared to the setup, which de-stresses at regular intervals.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115680230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reinforcement Learning-Based Guidance of Autonomous Vehicles 基于强化学习的自动驾驶车辆引导

2023 24th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2023-04-05 DOI: 10.1109/ISQED57927.2023.10129362

Joseph Clemmons, Yu-Fang Jin

{"title":"Reinforcement Learning-Based Guidance of Autonomous Vehicles","authors":"Joseph Clemmons, Yu-Fang Jin","doi":"10.1109/ISQED57927.2023.10129362","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129362","url":null,"abstract":"Reinforcement learning (RL) has attracted significant research efforts to guide an autonomous vehicle (AV) for a collision-free path due to its advantages in investigating interactions among multiple vehicles and dynamic environments. This study deploys a Deep Q-Network (DQN) based RL algorithm with reward shaping to control an ego AV in an environment with multiple vehicles. Specifically, the state space of the RL algorithm depends on the desired destination, the ego vehicle’s location and orientation, and the location of other vehicles in the system. The training time of the proposed RL algorithm is much shorter than most current image-based algorithms. The RL algorithm also provides an extendable framework to include a varying number of vehicles in the environment and can be easily adapted to different maps without changing the setup of the RL algorithm. Three scenarios were simulated in the Cars Learn to Act (CARLA) simulator to examine the effects of the proposed RL algorithm on guiding the ego AV interacting with multiple vehicles on straight and curvy roads. Our results showed that the ego AV could learn to reach its destination within 5000 episodes for all scenarios tested.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115684077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0