Mi-Sung Han, Jiwan Kim, Donggeon Kim, Hyunuk Jeong, Gilho Jung, Myeongwon Oh, Hyundong Lee, Yunjeong Go, Hyunwoo Kim, Jongbeom Kim, Taigon Song
{"title":"HFGCN: High-speed and Fully-optimized GCN Accelerator","authors":"Mi-Sung Han, Jiwan Kim, Donggeon Kim, Hyunuk Jeong, Gilho Jung, Myeongwon Oh, Hyundong Lee, Yunjeong Go, Hyunwoo Kim, Jongbeom Kim, Taigon Song","doi":"10.1109/ISQED57927.2023.10129340","DOIUrl":null,"url":null,"abstract":"graph convolutional network (GCN) is a type of neural network that inference new nodes based on the connectivity of the graphs. GCN requires high-calculation volume for processing, similar to other neural networks requiring significant calculation. In this paper, we propose a new hardware architecture for GCN that tackles the problem of wasted cycles during processing. We propose a new scheduler module that reduces memory access through aggregation and an optimized systolic array with improved delay. We compare our study with the state-of-the-art GCN accelerator and show outperforming results.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 24th International Symposium on Quality Electronic Design (ISQED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED57927.2023.10129340","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
graph convolutional network (GCN) is a type of neural network that inference new nodes based on the connectivity of the graphs. GCN requires high-calculation volume for processing, similar to other neural networks requiring significant calculation. In this paper, we propose a new hardware architecture for GCN that tackles the problem of wasted cycles during processing. We propose a new scheduler module that reduces memory access through aggregation and an optimized systolic array with improved delay. We compare our study with the state-of-the-art GCN accelerator and show outperforming results.