On-Interposer Decoupling Capacitors Placement for Interposer-based 3DIC

Abstract

With the demand for high performance and density, silicon interposer-based three-dimensional integrated circuit (3DIC) can be one of promising solutions for these requirements. However, simultaneously switching noise (SSN) will cause voltage fluctuation and hence performance degradation and logic failure might occur. Our work proposes an efficient Simulated Annealing (SA) based algorithm to perform decap placement automatically on the interposer. In our solution, target impedance can be achieved within certain frequency range. Results show that number of decaps as well as impedance of PDN are minimized to meet the requirement.