2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)最新文献

Adding Conditionality to Resilient Bundled-Data Designs 为弹性捆绑数据设计添加条件性

2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) Pub Date : 2016-05-08 DOI: 10.1109/ASYNC.2016.22

D. Hand, A. Katrin, W. Koven

引用次数: 2

Optimising Bundled-Data Balsa Circuits 优化捆绑数据Balsa电路

2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) Pub Date : 2016-05-08 DOI: 10.1109/ASYNC.2016.11

Norman Kluge, Ralf Wollowski

引用次数: 1

Efficient Metastability-Containing Gray Code 2-Sort 高效含亚稳的Gray码2-排序

2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) Pub Date : 2016-05-08 DOI: 10.1109/ASYNC.2016.18

C. Lenzen, Moti Medina

引用次数: 8

Low Power QDI Asynchronous FFT 低功耗QDI异步FFT

2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) Pub Date : 2016-05-08 DOI: 10.1109/ASYNC.2016.17

Benjamin Z. Tang, F. Lane

引用次数: 10

Specification Mining for Asynchronous Controllers 异步控制器的规范挖掘

2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) Pub Date : 2016-05-08 DOI: 10.1109/ASYNC.2016.10

Javier de San Pedro, Thomas Bourgeat, J. Cortadella

引用次数: 4

Qualifying Relative Timing Constraints for Asynchronous Circuits 确定异步电路的相对时序约束

2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) Pub Date : 2016-05-08 DOI: 10.1109/ASYNC.2016.23

Jotham Vaddaboina Manoranjan, K. Stevens

引用次数: 9

Ring Oscillator Clocks and Margins 环形振荡器时钟和边缘

2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) Pub Date : 2016-05-08 DOI: 10.1109/ASYNC.2016.14

J. Cortadella, Marc Lupon, A. Moreno-Conde, Antoni Roca, S. Sapatnekar

引用次数: 23

Fault Classification of the Error Detection Logic in the Blade Resilient Template 刀片弹性模板中检错逻辑的故障分类

2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) Pub Date : 2016-05-08 DOI: 10.1109/ASYNC.2016.9

F. Kuentzer, Alexandre M. Amory

{"title":"Fault Classification of the Error Detection Logic in the Blade Resilient Template","authors":"F. Kuentzer, Alexandre M. Amory","doi":"10.1109/ASYNC.2016.9","DOIUrl":"https://doi.org/10.1109/ASYNC.2016.9","url":null,"abstract":"Resilient architectures emerged as a promising solution to remove worst-case timing margins added due to process, voltage and temperature variation, improving system performance while reducing energy consumption. Asynchronous circuits can also improve energy efficiency and performance due to the absence of a global clock. A recently proposed circuit template, called Blade, leverages the advantages of both asynchronous and resilient techniques. However, Blade still presents challenges in terms of testing, which hinder its practical application. This paper evaluates the fault behavior of the Error Detection Logic (EDL) block of Blade with single stuck-at or propagation delay fault models. We propose a fault classification based on the effects observed in the overall circuit operation while in the presence of a fault. This classification shows the obtained fault coverage assuming three different testability scenarios and it also shows that a single fault can entirely disable an EDL, disabling its resilience. The proposed classification can be used in the future to improve the design for testability of resilient architectures.","PeriodicalId":314538,"journal":{"name":"2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)","volume":"692 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122493853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

The Metastable Behavior of a Schmitt-Trigger 施密特触发器的亚稳态行为

2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) Pub Date : 2016-05-08 DOI: 10.1109/ASYNC.2016.19

A. Steininger, Jürgen Maier, Robert Najvirt

{"title":"The Metastable Behavior of a Schmitt-Trigger","authors":"A. Steininger, Jürgen Maier, Robert Najvirt","doi":"10.1109/ASYNC.2016.19","DOIUrl":"https://doi.org/10.1109/ASYNC.2016.19","url":null,"abstract":"Schmitt-Trigger circuits are the method of choice for converting general signal shapes into clean, well-behaved digital ones. In this context these circuits are often used for metastability handling, as well. However, like any other positive feedback circuit, a Schmitt-Trigger can become metastable itself. Therefore, its own metastable behavior must be well understood, in particular the conditions that may cause its metastability. In this paper we will build on existing results from Marino to show that (a) a monotonic input signal can cause late transitions but never leads to a non-digital voltage at the Schmitt-Trigger output, and (b) a non-monotonic input can pin the Schmitt-Trigger output to a constant voltage at any desired (also non-digital) level for an arbitrary duration. In fact, the output can even be driven to any waveform within the dynamic limits of the system. We will base our analysis on a mathematical model of a Schmitt-Trigger's dynamic behavior and perform SPICE simulations to support our theory and confirm its validity for modern CMOS implementations. Furthermore, we will discuss several use cases of a Schmitt-Trigger in the light of our results.","PeriodicalId":314538,"journal":{"name":"2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131592147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Modeling and Analysis of Power Supply Noise Tolerance with Fine-Grained GALS Adaptive Clocks 细粒度GALS自适应时钟的电源噪声容限建模与分析

2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) Pub Date : 2016-05-08 DOI: 10.1109/ASYNC.2016.13

Divya Akella, Matthew R. Fojtik, Brucek Khailany, Sudhir S. Kudva, Yaping Zhou, B. Calhoun

{"title":"Modeling and Analysis of Power Supply Noise Tolerance with Fine-Grained GALS Adaptive Clocks","authors":"Divya Akella, Matthew R. Fojtik, Brucek Khailany, Sudhir S. Kudva, Yaping Zhou, B. Calhoun","doi":"10.1109/ASYNC.2016.13","DOIUrl":"https://doi.org/10.1109/ASYNC.2016.13","url":null,"abstract":"Power supply noise can significantly degrade circuit performance in modern high-performance SoCs. Adaptive clocking schemes have been proposed recently that can tolerate power supply noise by adjusting the clock frequency in response to fast-changing voltage variations. In this paper, we model and quantify power supply noise tolerance with a fine-grained globally asynchronous locally synchronous (GALS) design style together with an adaptive clocking scheme. An experimental setup that includes SPICE and Verilog-A models is used to quantify the effect of clock-tree insertion delay and spatial workload variations on power supply noise tolerance in both traditional synchronous adaptive clocking and a fine-grained GALS adaptive clocking scheme. Compared to the traditional scheme, fine-grained GALS adaptive clocking significantly reduces these effects and the margins required to tolerate power supply noise. The gain is quantified using the uncompensated voltage noise metric, which is defined as the additional voltage margin that is required for failure-free operation of circuits at the frequency dictated by the adaptive clocking scheme. In our experimental setup for a typical high performance SoC, fine-grained GALS adaptive clocking achieves a 78 mV saving in uncompensated voltage noise, which is an equivalent of 15% savings in power.","PeriodicalId":314538,"journal":{"name":"2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130746659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12