Optimising Bundled-Data Balsa Circuits

Balsa provides a design flow where asynchronous circuits are created from high-level specifications, but the syntax-driven translation often results in performance overhead. To improve this, we exploit the fact that bundled-data circuits can be divided into data and control path. Hence, tailored optimisation techniques can be applied to both paths separately. For control path optimisation, STG-based resynthesis has been introduced (applying logic minimisation). However, solid results are missing so far due to problems with state explosion and the reliable insertion of reset logic. To tackle this, we use an adjusted STG decomposition algorithm and started to develop a new logic synthesizer (based on ideas of petrify) with proper reset insertion. Adding the adapted data path, we are now able to get first promising post synthesis simulation results using an industrial technology library (with a performance improvement of up to 23%). First experiments show additional potential for performance improvements (of up to 56%) when standard tools for synchronous design are applied to the data path.