2016 IEEE AUTOTESTCON最新文献

{"title":"Testing high speed ethernet & fibre channel avionics switches","authors":"T. Troshynski","doi":"10.1109/AUTEST.2016.7589584","DOIUrl":"https://doi.org/10.1109/AUTEST.2016.7589584","url":null,"abstract":"Modern avionics systems are increasingly employing the use of high speed serial data networks. High capacity Ethernet and Fibre Channel switch fabrics are commonly found at the core of theses avionics networks and it is typical to find a mix of both copper and optical media interfaces as well as multiple data link bit rates within a single aircraft system. As these switching fabrics become integral pieces of avionic suites, functional test system must be developed with the capacity to replicate the combined data streams of multiple avionics end points when the fabric is off the aircraft and becomes the Unit Under Test (UUT). This paper provides a brief technical overview of the common principals of high speed avionics Ethernet and Fibre Channel networks and switch fabrics and also addresses several key items that must be addressed when designing a test and simulation system targeted to support high speed switch UUTs.","PeriodicalId":314357,"journal":{"name":"2016 IEEE AUTOTESTCON","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116075264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Diagnostic engineering in the 21st century: How do I optimize my analyses to solve real-world problems?","authors":"J. L. Amsell","doi":"10.1109/AUTEST.2016.7589612","DOIUrl":"https://doi.org/10.1109/AUTEST.2016.7589612","url":null,"abstract":"In the early days of Systems Engineering, several methods were developed in industry to verify or validate designs, ensure that products could meet requirements and specifications, and later support those products. Those methods consisted of techniques and methodologies considered state-of-the-art at the time. Sometimes, those approaches could not resolve all issues. For that reason, newer methods were developed to analyze and answer questions, but those newer methods did not really bring forth the necessary paradigm shift to supply optimal results. This paper will address that gap.","PeriodicalId":314357,"journal":{"name":"2016 IEEE AUTOTESTCON","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127097717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimization of core-based SOC test scheduling based on modified differential evolution algorithm","authors":"Deng Li-bao, Wei Debao, Qiao Liyan, Bian Xiaolong, Zhang Baoquan","doi":"10.1109/AUTEST.2016.7589602","DOIUrl":"https://doi.org/10.1109/AUTEST.2016.7589602","url":null,"abstract":"System on a chip (SOC) based on reusable IP core has been widely used in integrated circuit (IC) design and manufacturing. However SOC efficient test is still the bottle-neck issue. Test scheduling can enhance parallel test to minimize test application time at SOC system level. We present a modified differential evolution (MDE) approach to solve the problems of test scheduling and test access mechanism (TAM) partition for system on chips. A new hybrid mutation mechanism based on the probability estimation operator is introduced in the paper for better handling test scheduling, where the first variation coefficient stays the same but the second variation coefficient changes with iterative times. The different evolutionary strategies are adopted to accelerate effectively convergence without loss in population diversity as far as possible. Different mutation operators and evolutionary strategies are combined to get optimal results. The experimental results on ITC'02 SOC benchmarks are encouraging compared with the improved quantum-inspired evolutionary (IQI), genetic algorithm (GA), the integer linear programming formulation (ILP) and heuristic approaches.","PeriodicalId":314357,"journal":{"name":"2016 IEEE AUTOTESTCON","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127106743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Software-driven technology insertion strategies for automatic test systems","authors":"Mike Watts","doi":"10.1109/AUTEST.2016.7589609","DOIUrl":"https://doi.org/10.1109/AUTEST.2016.7589609","url":null,"abstract":"As Automatic Test Systems continue to adopt architectures based on synthetic instrumentation and modular I/O platforms, software is eclipsing hardware as the primary input for determining technology insertion cadence and scope. While abstracting Test Programs Sets from specific hardware is commonly referenced as a valuable tactic to reduce the risks of I/O obsolescence, it also requires significant up-front investment with a return that is later determined by the frequency of change. As systems become increasingly software-centric, a cost-optimized development strategy requires bounding technology insertion options, evaluating the costs associated with developing driver and measurement layers across those options, and managing the costs of migrating across application software and operating systems as a function of time. This paper will discuss the evolving solution space for software-dominated technology insertion strategies through an examination of the underlying compatibility of the COTS components at play.","PeriodicalId":314357,"journal":{"name":"2016 IEEE AUTOTESTCON","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129587023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Lost bus: Solving the obsolete PC bus standards problem in ATE","authors":"P. Gilenberg","doi":"10.1109/AUTEST.2016.7589617","DOIUrl":"https://doi.org/10.1109/AUTEST.2016.7589617","url":null,"abstract":"Every 6 to 11 years a new PC peripheral interface standard is developed. As the new interface gains in popularity, the old interfaces that are replaced become obsolete. This poses a challenge for ATE and UUT equipment that rely on the PC peripheral interfaces for testing. The solution for the obsolescence problem in PXI (and similar) systems is to move the interfaces away from the PC and into an instrument. A peripheral instrument would need to include several standard PC interfaces such as Ethernet, USB, SATA, UART, and I2C. By moving the interfaces to an instrument, when the PC and the associated interfaces become obsolete, the instrument can continue to be produced allowing the continued testing of the legacy UUTs. Furthermore, the instrument can maintain software compatibility through multiple OS releases preventing costly rehosts of TPS (Test Program Set).","PeriodicalId":314357,"journal":{"name":"2016 IEEE AUTOTESTCON","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128114688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Machine learning anomaly detection in large systems","authors":"J. Murphree","doi":"10.1109/AUTEST.2016.7589589","DOIUrl":"https://doi.org/10.1109/AUTEST.2016.7589589","url":null,"abstract":"We have a need for methods to efficiently determine the health of a system. Diagnostics and prognostics determine system heath through analysis of data from sensors. Anomalies in the data can help us determine if there is a failure or a pending failure. There are common statistical methods to detect anomalies in individual measurements. For systems with many measurements, the anomalies may occur as specific combinations of values. Large systems have various associated states and modes which define the valid measurements. The amount of data to analyze grows very quickly as the system becomes more complex. In recent years techniques have been developed to address large data analysis. Machine Learning encompasses a broad selection of tools to optimize a statistical model of the data. These tools include supervised learning techniques, such as linear regression and logistic regression, in which training data exists to tune the model. Unsupervised learning, such as clustering, is used to explore data which does not have a defined output label associated with inputs data. Standard approaches to training supervised learning systems require a large sample of positive and negative outcome data. Some uses of machine learning involve data where there are very few cases of negative outcomes. There are machine learning algorithms defined as Anomaly Detection which are designed to deal with this type of data. Simple algorithms include Gaussian Distribution Analysis, which assumes independence in distributions of data. Large Systems with anomalies defined in the dependent combinations of data require either a manual creation of combinations of independent variables, or Multivariate Gaussian Distribution Analysis, which does not scale well for large systems. A further complication is the mixture of linear and discrete data. Neural Networks are a type of learning system which has been applied to each of the individual needs addressed above. This paper describes an approach to anomaly detection using neural networks for the specific problems in large systems to efficiently determine system health.","PeriodicalId":314357,"journal":{"name":"2016 IEEE AUTOTESTCON","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130506223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and implementation of shared BISR for RAMs: A case study","authors":"G. Wang, Chengjuan Chang","doi":"10.1109/AUTEST.2016.7589621","DOIUrl":"https://doi.org/10.1109/AUTEST.2016.7589621","url":null,"abstract":"As transistors' sizes of embedded memory continue to shrink and the valuable silicon is becoming the draining resources, it is the prevalent trend that multi-memory structures exist in the current SOC design to achieve better performance. Due to the imperfect manufacturing processes, it may introduce the faults to the designs. Built-In Self-Test(BIST) and Self-Repair(BISR) are the better test and repair methods for embedded memory, however, to the single embedded memory, both BIST and BISR are unacceptable in multi-memory design and the redundancies resources in memories which manufacturers provide are very limited. It is inefficient to use the traditional redundancy resource allocation algorithms, instead of using a more precise BISR structure to improve both the repair rate of RAMs and the resource utilization of redundancies, as well as, reducing the silicon area overhead of BISR circuits. For these aims, this paper proposes a shared self-repair design that uses Context Addressable Memory(CAM) as the operation units of fault information. In the paper, it clearly presents the special components of design and the corresponding working principles. We implemented this structure in real industrial microprocessors. Experimental results demonstrate the effectiveness of the proposed structure.","PeriodicalId":314357,"journal":{"name":"2016 IEEE AUTOTESTCON","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131820991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Legacy test systems — Replace or maintain","authors":"J. Kent, M. Dewey","doi":"10.1109/AUTEST.2016.7589645","DOIUrl":"https://doi.org/10.1109/AUTEST.2016.7589645","url":null,"abstract":"Test platforms age, the components within the test systems degrade, become obsolete and wear out over time. Manufacturing companies must continuously evaluate the expected lifespan of their test equipment and determine the risk and tradeoffs associated with replacing the equipment vs. maintaining the equipment. Both industry and government entities continually struggle with how to best evaluate and address the issues of aging test equipment and systems. This paper reviews the various options available to test engineers when faced with replacing or maintaining a test system. Specifically, the manufacturing / test community must evaluate the consequences, risks and costs associated with each choice: 1. Do nothing and continue to maintain equipment until equipment failure. 2. Rejuvenate equipment by replacing components / instruments. 3. Replace existing equipment with modern automated test equipment. 4. Outsource manufacturing and test of product to a supplier. To help quantify the decision making process the use of an evaluation tool can help analyze the factors that influence the “replace or maintain” question. Each of the options listed above carries with it its own list of questions that must be addressed. These questions are encoded into the tool with responses then interpreted and results collated with user historical data, providing the test engineer with quantifiable and meaningful data for evaluating the cost of replacing or maintain factory test equipment. The following sections detail how this tool can be developed and utilized as part of the “replace or maintain” decisional process.","PeriodicalId":314357,"journal":{"name":"2016 IEEE AUTOTESTCON","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133920762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Utilization of the 5th generation mobile networks for automated tests","authors":"A. Guney, Halil Tongul","doi":"10.1109/AUTEST.2016.7589599","DOIUrl":"https://doi.org/10.1109/AUTEST.2016.7589599","url":null,"abstract":"Internet of things is one of the most important achievements that 5G is expected to bring. Todays LTE and LTE-A networks have limited number of connected users and also the latency introduced in these networks has a wide range. 5G is not only envisioned to provide faster data rates, but also introduce the possible connection of a huge number of devices and expected to reduce the latency significantly. Researchers estimate that 50 billion devices will be connected to the mobile networks within 5 years. Most of these devices will employ tasks that will be controlled from a remote host which requires a very small latency. Therefore, 5G is considered to be the near-perfect media for the internet of things concept. However, 5G as a hot topic, is still under research and there is a long way through realizing it. ASELSAN devoted a highly skilled team for the development of 5G base stations. As test engineers, we will be taking part in the development of 5G, however, in this paper we are not discussing about the tests of 5G networks. Rather we are inspecting the exploitation of 5G for global test scenarios. One possible application for internet of things can be thought as: multiple central or field test stations connected to the internet through 5G networks with low end-to-end latency, which are running test sequences from a cloud database and writing the results to the same database. Moreover, individual devices can connect to mobile networks and provide built-in test results to the same database, which exponentially increase the number of connected devices. In this paper, we are taking the first step towards realizing Internet of test stations. Since the number of test stations can be very high it is intractable to use local test sequences and update core test files manually. We have developed a new test software set that stores all the test sequences in a database and automatically updates the core setup files as needed. With this scheme, it will be very easy to bring all the test-related stuff to Internet. The main focus of the paper is on the design details of the new test executive software introduced.","PeriodicalId":314357,"journal":{"name":"2016 IEEE AUTOTESTCON","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127081297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Scalable and adaptive design test system for ground-based to airborne platforms","authors":"Tranchau Nguyen, T. Ung, Mark Reimann, Scott Rawlings, Heather Holmquist, Alexander Robinson","doi":"10.1109/AUTEST.2016.7589579","DOIUrl":"https://doi.org/10.1109/AUTEST.2016.7589579","url":null,"abstract":"This paper focuses on the scalable and adaptive design of building a test system to support multiple United States Air Force (USAF) systems while preserving the legacy capabilities (requirements) and initial investments (software/hardware) of those systems. From the Intercontinental Ballistic Missile (ICBM) Minuteman (MM) III Ground-Based Launch Control Support System (LCSS) such as the Ground Minuteman Automatic Test System (GMATS) to the ICBM MM III telemetry wafer processing effort like the Radio Frequency Test Set (RFTS) to airborne projects such as the F-16 Radar Transmitter Test System (RTTS) to the Original Equipment Manufacturers (OEMs) hardware testing for the F-16 Common Configuration Implementation Program (CCIP), each of these systems required a unique test station with specific hardware and, customized Test Executive Interface (TEI) and software programming languages to accomplish its tasks. Due to the rapid obsolescence of hardware and additional requirements from the end customers, the new replacement test system for current systems as GMATS/RFTS/RTTS/CCIP must have the adaptive capability in its hardware design, and agility, along with flexibility in its software design, to satisfy the requirements for the above systems and be architecturally scalable for other systems in the future with minimal impact to the legacy hardware interface adapters and software architecture to be cost effective, manageable and successful over the next 20+ years in a typical Department of Defense (DoD) weapon system.","PeriodicalId":314357,"journal":{"name":"2016 IEEE AUTOTESTCON","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130956671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}