Design and implementation of shared BISR for RAMs: A case study

Abstract

As transistors' sizes of embedded memory continue to shrink and the valuable silicon is becoming the draining resources, it is the prevalent trend that multi-memory structures exist in the current SOC design to achieve better performance. Due to the imperfect manufacturing processes, it may introduce the faults to the designs. Built-In Self-Test(BIST) and Self-Repair(BISR) are the better test and repair methods for embedded memory, however, to the single embedded memory, both BIST and BISR are unacceptable in multi-memory design and the redundancies resources in memories which manufacturers provide are very limited. It is inefficient to use the traditional redundancy resource allocation algorithms, instead of using a more precise BISR structure to improve both the repair rate of RAMs and the resource utilization of redundancies, as well as, reducing the silicon area overhead of BISR circuits. For these aims, this paper proposes a shared self-repair design that uses Context Addressable Memory(CAM) as the operation units of fault information. In the paper, it clearly presents the special components of design and the corresponding working principles. We implemented this structure in real industrial microprocessors. Experimental results demonstrate the effectiveness of the proposed structure.