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18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)最新文献

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Reliability characterizations of resistive switching devices using zinc oxide thin film 使用氧化锌薄膜的电阻开关器件的可靠性特性
18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2011-07-04 DOI: 10.1109/IPFA.2011.5992762
F. Chiu, Peng-Wei Li, W. Chang, Tai-bor Wu, Chih-Chi Chen, Chih-Yao Huang
{"title":"Reliability characterizations of resistive switching devices using zinc oxide thin film","authors":"F. Chiu, Peng-Wei Li, W. Chang, Tai-bor Wu, Chih-Chi Chen, Chih-Yao Huang","doi":"10.1109/IPFA.2011.5992762","DOIUrl":"https://doi.org/10.1109/IPFA.2011.5992762","url":null,"abstract":"In this work, Pt/ZnO/Pt capacitors were fabricated and investigated for nonvolatile memory applications. The memory devices exhibit inerratic and reproducible bipolar resistive switching characteristics. A forming electric field is required to induce the resistive switching property. The reliability characteristics of program/erase cycling endurance and data retention were measured. The high/low resistance states and specific set/reset voltages were examined by Weibull plots. In addition, the relationship between specific voltages and temperatures was also discussed.","PeriodicalId":312315,"journal":{"name":"18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114960248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Effects of dopings on the electric-field-induced atomic migration and void formation in Ge2Sb2Te5 掺杂对Ge2Sb2Te5中电场诱导原子迁移和空穴形成的影响
18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2011-07-04 DOI: 10.1109/IPFA.2011.5992717
Tae-Youl Yang, Ju-Young Cho, Yong-Jin Park, Young‐Chang Joo
{"title":"Effects of dopings on the electric-field-induced atomic migration and void formation in Ge2Sb2Te5","authors":"Tae-Youl Yang, Ju-Young Cho, Yong-Jin Park, Young‐Chang Joo","doi":"10.1109/IPFA.2011.5992717","DOIUrl":"https://doi.org/10.1109/IPFA.2011.5992717","url":null,"abstract":"Electromigration in molten and crystalline Ge2Sb2Te5 (GST) was characterized using pulsed DC stress to an isolated line structure. In the electomigration of molten GST, the effects of N-and Bi-doping on the electromigration were aslo studied to find the solution for inhibiting the electromigration. When a single pulse (∼10−3 s) was applied to the lines, both undoped and doped GST lines were melted by Joule heating, and Ge and Sb atoms migrate to the cathode, whereas Te atoms migrate to the anode. This elemental separation in the molten GST was caused by an electrostatic force-induced electromigration. The migration rate of the constituent atoms in the undoped GST was similar to that in Bi-doped GST, but was decreased by N-doping. Under applying a 10 MHz pulsed DC, the melting by Joule heating was inhibited, and electromigration in the crystalline state was detected. All constituent elements migrated to the cathode, which is originated from the electromigration by hole-windforce. This study provide the basic understanding about the degradation phenomena in phase change memory, and suggest the method for inhibiting the endurance failures.","PeriodicalId":312315,"journal":{"name":"18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125940246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Reconfiguration algorithm for low temperature sub-array on VLSI/WSI arrays with faults 故障VLSI/WSI阵列低温子阵列重构算法
18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2011-07-04 DOI: 10.1109/IPFA.2011.5992733
W. Jigang, Zhipeng Niu, Yuanbo Zhu, T. Srikanthan, Qingni Shen
{"title":"Reconfiguration algorithm for low temperature sub-array on VLSI/WSI arrays with faults","authors":"W. Jigang, Zhipeng Niu, Yuanbo Zhu, T. Srikanthan, Qingni Shen","doi":"10.1109/IPFA.2011.5992733","DOIUrl":"https://doi.org/10.1109/IPFA.2011.5992733","url":null,"abstract":"Temperature of the processing elements on integrated circuit threaten the reliability and performance of a hard real-time system. This paper presents a temperature-aware algorithm to reconfigure two-dimensional m × n VLSI/WSI arrays linked by 4-port switches in the presence of faulty processing elements. Based on dynamic programming, the proposed algorithm constructs each logical column with the lowest temperature for a cool target array on a given host array. Simulation results show that the temperature of target array is reduced without loss of harvest in comparison to the state-of-the-art.","PeriodicalId":312315,"journal":{"name":"18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"648 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133171535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Unipolar resistive switching and retention of RTA-treated zinc oxide (ZnO) resistive RAM rta处理氧化锌(ZnO)阻性RAM的单极电阻开关和保持
18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2011-07-04 DOI: 10.1109/IPFA.2011.5992754
Cheng-li Lin, Shu-Ching Wu, Chi-Chang Tang, Y. Lai, Syuan-Ren Yang, Shich-Chuan Wu
{"title":"Unipolar resistive switching and retention of RTA-treated zinc oxide (ZnO) resistive RAM","authors":"Cheng-li Lin, Shu-Ching Wu, Chi-Chang Tang, Y. Lai, Syuan-Ren Yang, Shich-Chuan Wu","doi":"10.1109/IPFA.2011.5992754","DOIUrl":"https://doi.org/10.1109/IPFA.2011.5992754","url":null,"abstract":"This work investigates the effects of N2 RTA treatment on characteristics of ZnO film as resistive RAM (RRAM). In addition, we also study the leakage current behavior and conducting mechanism in the low resistance state (LRS) and high resistance state (HRS) of ZnO RRAM. From the electrical characteristics, the resistance ratio (HRS/LRS) can be larger than 1011, and the set and reset voltage is lower to around 0.3V and 2.2V, respectively. The RTA-treated ZnO RRAM reveals more improvement on the endurance up to 103 times. Presumably, the RTA treatment will induce more crystalline phases in ZnO film and rearranges and/or recover the oxygen vacancies and distribution in the film, and it is beneficial for the resistance switching. Low power and high resistance ratio (HRS/LRS) of ZnO RRAM can be finished for the RTA-treated ZnO RRAM with inexpensive Al metal electrode.","PeriodicalId":312315,"journal":{"name":"18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117324290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A novel method to analyze analog and mixed mode IC failure by Soft Defect Localization (SDL) 基于软缺陷定位(SDL)的模拟和混合模式集成电路故障分析新方法
18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2011-07-04 DOI: 10.1109/IPFA.2011.5992712
Jinglong Li, L. Zhai, Winter Wang, M. Motohiko, Bird Fan, Andy Zhang
{"title":"A novel method to analyze analog and mixed mode IC failure by Soft Defect Localization (SDL)","authors":"Jinglong Li, L. Zhai, Winter Wang, M. Motohiko, Bird Fan, Andy Zhang","doi":"10.1109/IPFA.2011.5992712","DOIUrl":"https://doi.org/10.1109/IPFA.2011.5992712","url":null,"abstract":"In semiconductor failure analysis, Soft Defect Localization (SDL) technology is applied to localize defect that dependent on conditions such as temperature, frequency, voltage. SDL is usually used for digital failure analysis. However, to directly apply SDL in analog part is not so common. In this paper, a novel method is introduced to analyze analog signal failure at high temperature by SDL technology.","PeriodicalId":312315,"journal":{"name":"18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125132817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Multi variation mapping for Dynamic Laser Stimulation analysis 动态激光刺激分析的多变分映射
18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2011-07-04 DOI: 10.1109/IPFA.2011.5992785
S. Kevin, P. Perdu
{"title":"Multi variation mapping for Dynamic Laser Stimulation analysis","authors":"S. Kevin, P. Perdu","doi":"10.1109/IPFA.2011.5992785","DOIUrl":"https://doi.org/10.1109/IPFA.2011.5992785","url":null,"abstract":"Dynamic Laser Stimulation is now widely used for soft defect issues and is generally based on the study of device under test functionality (pass or fail). Automatic Test Equipments (ATE) are able to collect a lot of electrical parameters about device under test status but actually only the pass/fail is exploited and mapped has function of the laser beam position. Multi variation mapping (MVM) for Dynamic Laser Stimulation analysis gives the possibility to get all the data in same time than pass/fail and is able in one acquisition to give one mapping per data. Therefore MVM for Dynamic Laser Stimulation analysis offers the unique opportunity of collecting in one scan all the data necessary for a deep integrated circuit analysis.","PeriodicalId":312315,"journal":{"name":"18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124062965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Application of Wright Etch in failure analysis on localized abnormal implant profile in wafer fabrication Wright蚀刻技术在晶圆制造中局部异常晶圆轮廓失效分析中的应用
18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2011-07-04 DOI: 10.1109/IPFA.2011.5992757
W.F. Lee, A. Chin, P.H. Seah
{"title":"Application of Wright Etch in failure analysis on localized abnormal implant profile in wafer fabrication","authors":"W.F. Lee, A. Chin, P.H. Seah","doi":"10.1109/IPFA.2011.5992757","DOIUrl":"https://doi.org/10.1109/IPFA.2011.5992757","url":null,"abstract":"In this paper, four low yield cases related to implantation issues in semiconductor wafer fabrication process on Si CMOS device were presented. Wright Etch method was shown to be effective in localizing non-uniform implantation and detecting abnormal implant profile in the Si active area. The etch depth profile and surface morphology after Wright Etch were used primarily to determine any abnormality in the implantation. This method has been demonstrated useful for top view planar inspection using scanning electron microscope (SEM)","PeriodicalId":312315,"journal":{"name":"18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122833800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
DRAM failure cases under hot-carrier injection 热载流子注入下的DRAM故障案例
18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2011-07-04 DOI: 10.1109/IPFA.2011.5992747
S. Baeg, P. Chia, S. Wen, R. Wong
{"title":"DRAM failure cases under hot-carrier injection","authors":"S. Baeg, P. Chia, S. Wen, R. Wong","doi":"10.1109/IPFA.2011.5992747","DOIUrl":"https://doi.org/10.1109/IPFA.2011.5992747","url":null,"abstract":"In IIRW 2010, we presented new reliability stress methods (a.k.a. one ROW fast access) for dynamic random access memory (DRAM) hot-carrier injection (HCI) robustness qualifications [3]. In IRPS 2011, we presented the systematic simulation methodology for DRAM HCI robustness [4]. This is the follow-up paper for our two previous papers. We wrote our two previous papers because we experienced DRAM field failures due to HCI weakness. Due to the nature of the HCI failure mechanisms, physical failures were not visually inspected and visual based approach was not effective. This paper will provide different DRAM failure modes, all attributed to HCI as a root cause. Since we have to use the electrical failure analysis method, we believe it is important to document the method, the affected circuit, and the system signatures for the industrial community.","PeriodicalId":312315,"journal":{"name":"18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"AES-12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126527654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
The streched-exponential dependence of VT shift by gate bias and temperature stress in undoped Ge nanowire 未掺杂锗纳米线中栅极偏置和温度应力对VT位移的指数依赖关系
18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2011-07-04 DOI: 10.1109/IPFA.2011.5992768
Sungwon Yoo, Hyunseung Lee, M. Jo, Jong-Ho Lee
{"title":"The streched-exponential dependence of VT shift by gate bias and temperature stress in undoped Ge nanowire","authors":"Sungwon Yoo, Hyunseung Lee, M. Jo, Jong-Ho Lee","doi":"10.1109/IPFA.2011.5992768","DOIUrl":"https://doi.org/10.1109/IPFA.2011.5992768","url":null,"abstract":"We study I-V characteristics and time dependence of ΔV<inf>T</inf> under different V<inf>GS</inf>, temperature stresses and recovery in undoped back-gated Ge nanowire. We show that charge trapping is dominant mechanism of V<inf>GS</inf>, temperature stress and recovery by fitting measured ΔV<inf>T</inf> with stretched-exponential equation.","PeriodicalId":312315,"journal":{"name":"18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125524803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low voltage detection methods by microcolumn 微柱低压检测方法
18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2011-07-04 DOI: 10.1109/IPFA.2011.5992786
S. Choi, S. Babin, T. Oh, D. W. Kim, S. Ahn, H. S. Kim
{"title":"Low voltage detection methods by microcolumn","authors":"S. Choi, S. Babin, T. Oh, D. W. Kim, S. Ahn, H. S. Kim","doi":"10.1109/IPFA.2011.5992786","DOIUrl":"https://doi.org/10.1109/IPFA.2011.5992786","url":null,"abstract":"Low voltage microcolumn operated by less than 1keV beam energy and having high probe beam current can readily obtain low voltage images without bias voltages to sample. It has the main advantage of obtaining the information concentrated on thin surface layers, and can also obtain sample current images from sample without any detection devices. A sample current image has been analyzed using commercial Monte Carlo software.","PeriodicalId":312315,"journal":{"name":"18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125741042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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