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2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)最新文献

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Distributed-neuron-network based machine learning on smart-gateway network towards real-time indoor data analytics 基于分布式神经网络的智能网关网络机器学习，面向实时室内数据分析
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0531
Hantao Huang, Yuehua Cai, Hao Yu
{"title":"Distributed-neuron-network based machine learning on smart-gateway network towards real-time indoor data analytics","authors":"Hantao Huang, Yuehua Cai, Hao Yu","doi":"10.3850/9783981537079_0531","DOIUrl":"https://doi.org/10.3850/9783981537079_0531","url":null,"abstract":"Indoor data analytics is one typical example of ambient intelligence with behaviour or feature extraction from environmental data. It can be utilized to help improve comfort level in building and room for occupants. To address dynamic ambient change in a large-scaled space, real-time and distributed data analytics is required on sensor (or gateway) network, which however has limited computing resources. This paper proposes a computationally efficient data analytics by distributed-neuron-network (DNN) based machine learning with application for indoor positioning. It is based on one incremental L2-norm based solver for learning collected WiFi-data at each gateway and is further fused for all gateways in the network to determine the location. Experimental results show that with multiple distributed gateways running in parallel, the proposed algorithm can achieve 50x and 38x speedup during data testing and training time respectively with comparable positioning accuracy, when compared to traditional support vector machine (SVM) method.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128375082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A fine-grained performance model for GPU architectures GPU架构的细粒度性能模型
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0357
N. Bombieri, F. Busato, F. Fummi
{"title":"A fine-grained performance model for GPU architectures","authors":"N. Bombieri, F. Busato, F. Fummi","doi":"10.3850/9783981537079_0357","DOIUrl":"https://doi.org/10.3850/9783981537079_0357","url":null,"abstract":"The increasing programmability, performance, and cost/effectiveness of GPUs have led to a widespread use of such many-core architectures to accelerate general purpose applications. Nevertheless, tuning applications to efficiently exploit the GPU potentiality is a very challenging task, especially for inexperienced programmers. This is due to the difficulty of developing a SW application for the specific GPU architectural configuration, which includes managing the memory hierarchy and optimizing the execution of thousands of concurrent threads while maintaining the semantic correctness of the application. Even though several profiling tools exist, which provide programmers with a large number of metrics and measurements, it is often difficult to interpret such information for effectively tuning the application. This paper presents a performance model that allows accurately estimating the potential performance of the application under tuning on a given GPU device and, at the same time, it provides programmers with interpretable profiling hints. The paper shows the results obtained by applying the proposed model for profiling commonly used primitives and real codes.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134099368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Sampling-based buffer insertion for post-silicon yield improvement under process variability 在工艺可变性下，基于采样的后硅良率改进缓冲器插入
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0250
Grace Li Zhang, Bing Li, Ulf Schlichtmann
{"title":"Sampling-based buffer insertion for post-silicon yield improvement under process variability","authors":"Grace Li Zhang, Bing Li, Ulf Schlichtmann","doi":"10.3850/9783981537079_0250","DOIUrl":"https://doi.org/10.3850/9783981537079_0250","url":null,"abstract":"At submicron manufacturing technology nodes process variations affect circuit performance significantly. This trend leads to a large timing margin and thus overdesign to maintain yield. To combat this pessimism, post-silicon clock tuning buffers can be inserted into circuits to balance timing budgets of critical paths with their neighbors. After manufacturing, these clock buffers can be configured for each chip individually so that chips with timing failures may be rescued to improve yield. In this paper, we propose a sampling-based method to determine the proper locations of these buffers. The goal of this buffer insertion is to reduce the number of buffers and their ranges, while still maintaining a good yield improvement. Experimental results demonstrate that our algorithm can achieve a significant yield improvement (up to 35%) with only a small number of buffers.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134445272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A self-adaptive approach to efficiently manage energy and performance in tomorrow's heterogeneous computing systems 在未来的异构计算系统中有效管理能源和性能的自适应方法
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0986
E. Trainiti, Gianluca Durelli, A. Miele, C. Bolchini, M. Santambrogio
{"title":"A self-adaptive approach to efficiently manage energy and performance in tomorrow's heterogeneous computing systems","authors":"E. Trainiti, Gianluca Durelli, A. Miele, C. Bolchini, M. Santambrogio","doi":"10.3850/9783981537079_0986","DOIUrl":"https://doi.org/10.3850/9783981537079_0986","url":null,"abstract":"ICT adoption rate boomed during the last decades as well as the power consumption footprint that generates from those technologies. This footprint is expected to more than triple by 2020. Moreover, we are moving towards an on-demand computing scenario, characterized by varying workloads, constituted of diverse applications with different performance requirements, and criticality. A promising approach to address the challenges posed by this scenario is to better exploit specialized computing resources integrated in a heterogeneous system architecture (HSA) by taking advantage of their individual characteristics to optimize the performance/energy trade-off of the overall system. Better exploitation although comes with higher complexity. System architects need to take into account the efficiency of systems units, i.e. GPP(s) either alone or with a single family of accelerators (e.g., GPUs or FPGAs), as well as the applications workload, which often leads to inefficiency in their exploitation, and therefore in performance/energy. The work presented in this paper will address these limitations by exploiting self-adaptivity to allow the system to autonomously decide which specialized resource to exploit for a carbon footprint reduction, due to a more effective execution of the application, optimizing goals that the user can set (e.g., performance, energy, reliability).","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134488069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Optimizing Majority-Inverter Graphs with functional hashing 优化多数逆变器图与功能哈希
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0281
Mathias Soeken, L. Amarù, P. Gaillardon, G. Micheli
{"title":"Optimizing Majority-Inverter Graphs with functional hashing","authors":"Mathias Soeken, L. Amarù, P. Gaillardon, G. Micheli","doi":"10.3850/9783981537079_0281","DOIUrl":"https://doi.org/10.3850/9783981537079_0281","url":null,"abstract":"A Majority-Inverter Graph (MIG) is a recently introduced logic representation form whose algebraic and Boolean properties allow for efficient logic optimization. In particular, when considering logic depth reduction, MIG algorithms obtained significantly superior synthesis results as compared to the state-of-the-art approaches based on AND-inverter graphs and commercial tools. In this paper, we present a new MIG optimization algorithm targeting size minimization based on functional hashing. The proposed algorithm makes use of minimum MIG representations which are precomputed for functions up to 4 variables using an approach based on Satisfiability Modulo Theories (SMT). Experimental results show that heavily-optimized MIGs can be further minimized also in size, thanks to our proposed methodology. When using the optimized MIGs as starting point for technology mapping, we were able to improve both depth and area for the arithmetic instances of the EPFL benchmarks beyond the current results achievable by state-of-the-art logic synthesis algorithms.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130290442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Workload-aware power optimization strategy for asymmetric multiprocessors 非对称多处理器的工作负载感知功耗优化策略
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0253
Emanuele Del Sozzo, Gianluca Durelli, E. Trainiti, A. Miele, M. Santambrogio, C. Bolchini
{"title":"Workload-aware power optimization strategy for asymmetric multiprocessors","authors":"Emanuele Del Sozzo, Gianluca Durelli, E. Trainiti, A. Miele, M. Santambrogio, C. Bolchini","doi":"10.3850/9783981537079_0253","DOIUrl":"https://doi.org/10.3850/9783981537079_0253","url":null,"abstract":"Asymmetric multi-core architectures, such as the ARM big.LITTLE, are emerging as successful solutions for the embedded and mobile markets due to their capabilities to trade-off performance and power consumption. However, both the Heterogeneous Multi-Processing (HMP) scheduler integrated in the commercial products and the previous research approaches are not able to fully exploit such potentiality. We propose a new runtime resource management policy for the big. LITTLE architecture integrated in Linux aimed at optimizing the power consumption while fulfilling performance requirements specified for the running applications. Experimental results show an improvement of the 11% on the performance and at the same time 8% in peak power consumption w.r.t. the current Linux HMP solution.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122467886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Thermal-aware TSV repair for electromigration in 3D ICs 三维集成电路中电迁移的热感知TSV修复
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0726
Shengcheng Wang, M. Tahoori, K. Chakrabarty
{"title":"Thermal-aware TSV repair for electromigration in 3D ICs","authors":"Shengcheng Wang, M. Tahoori, K. Chakrabarty","doi":"10.3850/9783981537079_0726","DOIUrl":"https://doi.org/10.3850/9783981537079_0726","url":null,"abstract":"Electromigration (EM) occurrence on through-silicon-vias (TSVs) is a major reliability concern for Three-Dimensional Integrated-Circuits (3D ICs), and EM can severely reduce the mean-time-to-failure (MTTF). In this work, a novel fault tolerant technique is proposed to increase the MTTF of the functional TSV network through the assignment of spare TSVs to EM-vulnerable functional TSVs. The objective is to meet the target MTTF with minimum spare TSVs and minimal impact on the circuit timing. By considering the impact of temperature variation, the proposed technique provides a more robust repair solution for EM-induced TSV defects with minimum delay overhead, compared to previous thermal-unaware methods.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129151676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A procedure for improving the distribution of congestion in global routing 改进全局路由中拥塞分布的程序
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0732
Daohang Shi, A. Davoodi, Jeff T. Linderoth
{"title":"A procedure for improving the distribution of congestion in global routing","authors":"Daohang Shi, A. Davoodi, Jeff T. Linderoth","doi":"10.3850/9783981537079_0732","DOIUrl":"https://doi.org/10.3850/9783981537079_0732","url":null,"abstract":"This work introduces a procedure which takes as input a global routing solution that is already improved for routability based on the traditional total overflow (TOF) metric, and then improves the distribution of congestion without increasing the TOF. Our router is able to significantly decrease the number of edges in undesirable ranges of congestion by optimizing a convex piece-wise linear penalty function. The penalties are flexible and may be specified by the user. In our experiments, using the already-optimized global routing solutions of the ISPD'11 benchmarks-mostly have 0 units of TOF-we show the number of edges which are utilized very close to capacity can be significantly reduced. This work is the first to explicitly target improving the distribution of edge congestion corresponding to an already-optimized global routing solution without sacrificing the TOF.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128554931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Guarantees for runnable entities with heterogeneous real-time requirements 对具有异构实时需求的可运行实体的保证
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0247
Leonie Ahrendts, Zain Alabedin Haj Hammadeh, R. Ernst
{"title":"Guarantees for runnable entities with heterogeneous real-time requirements","authors":"Leonie Ahrendts, Zain Alabedin Haj Hammadeh, R. Ernst","doi":"10.3850/9783981537079_0247","DOIUrl":"https://doi.org/10.3850/9783981537079_0247","url":null,"abstract":"Classical real-time (RT) analysis proves temporal properties of tasks. In industrial practice, however, tasks are often composed of runnable entities with heterogeneous RT requirements. If RT guarantees are only available at task granularity, the strictest RT requirement of a runnable entity determines the RT requirement of the entire task. However, by giving RT guarantees for each runnable entity, this over-provisioning can be avoided. We provide an analysis which is fine-grained enough to provide hard and weakly-hard response time guarantees for runnable entities and show the improvement in an industrial case study.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114442463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Proposal for fast directional energy interchange used in MCMC-based autonomous decentralized mechanism toward resilient microgrid 基于mcmc的弹性微电网自主分散机制中快速定向能量交换方案
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0618
Yusuke Sakumoto, Ittetsu Taniguchi
{"title":"Proposal for fast directional energy interchange used in MCMC-based autonomous decentralized mechanism toward resilient microgrid","authors":"Yusuke Sakumoto, Ittetsu Taniguchi","doi":"10.3850/9783981537079_0618","DOIUrl":"https://doi.org/10.3850/9783981537079_0618","url":null,"abstract":"Microgrid is well known as key technology to improve renewable energy's ease of use. Some previous works focused on a microgrid that is divided into autonomous electricity subsystems (AESs) for its reliability and scalability. We have proposed the MCMC-based autonomous decentralized mechanism (ADM) to perform energy interchange between AESs so as to be supply energy appropriately for different energy demands among AESs. In this paper, toward resilient of microgrids, we design a method to realize directional energy interchange in our ADM on the basis of the convection diffusion. We investigate the effectiveness of the proposed method through simulation experiment considering energy shortage and emergency situations. We clarify that the proposed method can fast supply energy from external power grid to a microgrid under energy shortage situation, and can fast gather distributed energy to a specific AES (e.g., safe shelter) under emergency situation.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127049306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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