2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)最新文献_第8页

Automatic generation of power state machines through dynamic mining of temporal assertions 通过动态挖掘时态断言自动生成功率状态机

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0278

Alessandro Danese, G. Pravadelli, Ivan Zandona

{"title":"Automatic generation of power state machines through dynamic mining of temporal assertions","authors":"Alessandro Danese, G. Pravadelli, Ivan Zandona","doi":"10.3850/9783981537079_0278","DOIUrl":"https://doi.org/10.3850/9783981537079_0278","url":null,"abstract":"Several papers propose approaches based on power state machines (PSMs) for modelling and simulating the power consumption of system-on-chips (SoCs). However, while they focus on the use of PSMs as the underlying formalism for implementing dynamic power management techniques, they generally do not deal with the basic problem of generating PSMs. In most of these papers, PSMs just exist, in some cases they are manually defined, and only a few approaches give a hint of semiautomatic generation, but no fully-automatic approach exists in the literature. Indeed, without an automatic procedure, an accurate power characterization of complex SoCs by using PSMs is almost impossible. Thus, in this paper, first a methodology for the automatic generation of PSMs is proposed, and then, a statistical approach based on a Hidden Markov Model is presented for their simulation. The core of the approach is based on a mining procedure whose role consists of extracting temporal assertions describing the functional behaviours of the IP, which are then automatically mapped on states of the PSMs and characterized from the energy consumption point of view.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116477213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

RECORD: Reducing register traffic for checkpointing in embedded processors 记录:减少嵌入式处理器中检查点的寄存器流量

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0191

Tuo Li, Jude Angelo Ambrose, S. Parameswaran

{"title":"RECORD: Reducing register traffic for checkpointing in embedded processors","authors":"Tuo Li, Jude Angelo Ambrose, S. Parameswaran","doi":"10.3850/9783981537079_0191","DOIUrl":"https://doi.org/10.3850/9783981537079_0191","url":null,"abstract":"Checkpoint/recovery, as a classic method, has been widely used for overcoming transient faults in computing systems. The basic function of checkpoint/recovery is to save the system states periodically and to restore the system states by using the saved states if a fault occurs. With the hardware-implemented checkpointing mechanism executing at runtime, a processor will have substantially increased register-file reads. For embedded processors, which typically have restricted design constraints on area, power, and performance, such increases might compromise the quality of the application greatly. In this paper, we present a checkpointing method, RECORD, aimed at reducing the resultant register traffic at runtime, by leveraging register data dependencies. The proposed checkpointing method can reduce redundant executions of register-file checkpointing. The experiments show that RECORD achieves improved register traffic reduction (20%) along with reduced dynamic power consumption (approximately 20%) in comparison to the state of the art with minimal area overhead. The leakage power increases marginally (about 2%), but is more than compensated by the decrease in dynamic power.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116354878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Validating scheduling transformation for behavioral synthesis 验证行为综合的调度转换

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0501

Zhenkun Yang, K. Hao, Kai Cong, Li Lei, S. Ray, Fei Xie

引用次数: 3

All-digital hybrid-control buck converter for Integrated Voltage Regulator applications 用于集成稳压器应用的全数字混合控制降压变换器

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0320

Ta-Tung Yen, Bin Yu, V. Sathe

{"title":"All-digital hybrid-control buck converter for Integrated Voltage Regulator applications","authors":"Ta-Tung Yen, Bin Yu, V. Sathe","doi":"10.3850/9783981537079_0320","DOIUrl":"https://doi.org/10.3850/9783981537079_0320","url":null,"abstract":"As power-dissipation remains a roadblock to maintaining growth in computational performance, the trend toward increasingly aggressive reliance on Dynamic Voltage and Frequency Scaling (DVFS) by power power management systems, and Integrated Voltage Regulation (IVR) in particular, will continue. As voltage domains continue to shrink, and an increasing number of Voltage Regulators (VRs) are employed within a System-on- Chip (SoC), all-digital buck converters will become increasingly important from a scalability, portability, and system-methodology perspective. In addition to the existing challenges facing VR Modules, IVRs face additional efficiency and transient response challenges. In this paper, we propose a voltage-reference-free all-digital hybrid-control buck converter addressing these challenges through novel techniques for accurate digital derivative measurement for PID control, and fast, all-digital non-linear control for minimizing voltage droop. Simulations in 65nm CMOS demonstrate an 86% efficient, stable operation with fast transient response. A single-phase implementation using package mounted inductor and filter capacitor models achieves a 25mV droop for a 5A load current ramp at 500mA/ns.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127961227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hardware accelerator for analytics of sparse data 用于稀疏数据分析的硬件加速器

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0766

E. Nurvitadhi, Asit K. Mishra, Yu Wang, Ganesh Venkatesh, Debbie Marr

引用次数: 19

Run-time phase prediction for a reconfigurable VLIW processor 可重构VLIW处理器的运行时相位预测

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0644

Qi Guo, A. L. Sartor, Anthony Brandon, A. C. S. Beck, Xuehai Zhou, Stephan Wong

{"title":"Run-time phase prediction for a reconfigurable VLIW processor","authors":"Qi Guo, A. L. Sartor, Anthony Brandon, A. C. S. Beck, Xuehai Zhou, Stephan Wong","doi":"10.3850/9783981537079_0644","DOIUrl":"https://doi.org/10.3850/9783981537079_0644","url":null,"abstract":"It is well-known that different applications exhibit varying amounts of ILP. Execution of these applications on the same fixed-width VLIW processor will result (1) in wasted energy due to underutilized resources if the issue-width of the processor is larger than the inherent ILP; or alternatively, (2) in lower performance if the issue-width is smaller than the inherent ILP. Moreover, even within a single application distinct phases can be observed with varying ILP and therefore changing resource requirements. With this in mind, we designed the ρ-VEX processor, which is a VLIW processor that can change its issue-width at run-time. In this paper, we propose a novel scheme to dynamically (i.e., at run-time) optimize the resource utilization by predicting and matching the number of active data-paths for each application phase. The purpose is to achieve low energy consumption for applications with low ILP, and high performance for applications with high ILP, on a single VLIW processor design. We prototyped the ρ-VEX processor on an FPGA and obtained the dynamic traces of applications running on top of a Linux port. Our results show that it is possible in some cases to achieve the performance of an 8-issue core with 10% lower energy consumption, while in others we achieve the energy consumption of a 2-issue core with close to 20% lower execution time.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129120923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Activation of logic encrypted chips: Pre-test or post-test? 逻辑加密芯片的激活:前测还是后测?

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0687

Muhammad Yasin, S. Saeed, J. Rajendran, O. Sinanoglu

{"title":"Activation of logic encrypted chips: Pre-test or post-test?","authors":"Muhammad Yasin, S. Saeed, J. Rajendran, O. Sinanoglu","doi":"10.3850/9783981537079_0687","DOIUrl":"https://doi.org/10.3850/9783981537079_0687","url":null,"abstract":"Logic encryption has been a popular defense against Intellectual Property (IP) piracy, hardware Trojans, reverse engineering, and IC overproduction. It protects a design from these threats by inserting key-gates that break the functionality when controlled by wrong keys. Researchers have taken multiple attempts in breaking logic encryption and leaking its secret key, while they also proposed difficult-to-break logic encryption techniques. Mainly, state-of-the-art logic encryption techniques pursue two different models that differ in when the manufactured chips are activated by loading the secret key on the chip's memory: activation prior to manufacturing test (pre-test) versus subsequent to manufacturing test (post-test). In this paper, we shed light on the interaction between manufacturing test and logic encryption. We assess and compare the pre-test and post-test activation models not only in terms of the impact of logic encryption on test parameters such as fault coverage, test pattern count and test power consumption, but also in terms of the impact of manufacturing test on the security of logic encryption. We outline a test data mining attack that can successfully determine the logic encryption key of a pre-test activated chip by utilizing the test data.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130729299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 56

ECOSCALE: Reconfigurable computing and runtime system for future exascale systems ECOSCALE:用于未来百亿亿级系统的可重构计算和运行时系统

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_1021

I. Mavroidis, I. Papaefstathiou, L. Lavagno, Dimitrios S. Nikolopoulos, Dirk Koch, J. Goodacre, I. Sourdis, Vassilis D. Papaefstathiou, M. Coppola, Manuel Palomino

{"title":"ECOSCALE: Reconfigurable computing and runtime system for future exascale systems","authors":"I. Mavroidis, I. Papaefstathiou, L. Lavagno, Dimitrios S. Nikolopoulos, Dirk Koch, J. Goodacre, I. Sourdis, Vassilis D. Papaefstathiou, M. Coppola, Manuel Palomino","doi":"10.3850/9783981537079_1021","DOIUrl":"https://doi.org/10.3850/9783981537079_1021","url":null,"abstract":"In order to reach exascale performance, current HPC systems need to be improved. Simple hardware scaling is not a feasible solution due to the increasing utility costs and power consumption limitations. Apart from improvements in implementation technology, what is needed is to refine the HPC application development flow as well as the system architecture of future HPC systems. ECOSCALE tackles these challenges by proposing a scalable programming environment and architecture, aiming to substantially reduce energy consumption as well as data traffic and latency. ECOSCALE introduces a novel heterogeneous energy-efficient hierarchical architecture, as well as a hybrid many-core+OpenCL programming environment and runtime system. The ECOSCALE approach is hierarchical and is expected to scale well by partitioning the physical system into multiple independent Workers (i.e. compute nodes). Workers are interconnected in a tree-like fashion and define a contiguous global address space that can be viewed either as a set of partitions in a Partitioned Global Address Space (PGAS), or as a set of nodes hierarchically interconnected via an MPI protocol. To further increase energy efficiency, as well as to provide resilience, the Workers employ reconfigurable accelerators mapped into the virtual address space utilizing a dual stage System Memory Management Unit with coherent memory access. The architecture supports shared partitioned reconfigurable resources accessed by any Worker in a PGAS partition, as well as automated hardware synthesis of these resources from an OpenCL-based programming model.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116766244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 41

Availability and interpretability of optimal control for criticality estimation in vehicle active safety 车辆主动安全临界估计最优控制的可用性和可解释性

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_1033

S. Herrmann, W. Utschick

{"title":"Availability and interpretability of optimal control for criticality estimation in vehicle active safety","authors":"S. Herrmann, W. Utschick","doi":"10.3850/9783981537079_1033","DOIUrl":"https://doi.org/10.3850/9783981537079_1033","url":null,"abstract":"Current and future vehicular active safety systems rely on situation interpretation algorithms for mapping sensor information of the environment to a criticality or threat value. In dangerous driving situations, these metrics are used to trigger a range of safety interventions from warning the driver, pre-tensioning of the braking system, automatic emergency braking, and automatic emergency braking and steering. For highly complex functions like automatic braking and steering, validation through real-world test drives become increasingly costly and time-consuming. Here, simulation studies can be used, where a large set of dangerous driving scenarios is labeled with a reference criticality, that should represent the true criticality. In order to find such a ground truth criticality, we propose an optimal control formulation of criticality taking into account a vehicle dynamics model as well as lane constraints. Further, using stochastically generated driving scenes, we explore the tradeoff between different goal functions and constraint formulations for interpretability and convergence of the criticality measure in simulation scenarios.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131166833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

The Programmable Logic-in-Memory (PLiM) computer 可编程逻辑内存(PLiM)计算机

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0970

P. Gaillardon, L. Amarù, A. Siemon, E. Linn, R. Waser, A. Chattopadhyay, G. Micheli

引用次数: 146