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Optimising Power-Performance in SOI-based Null Convention Logic 基于soi的零约定逻辑的功率性能优化
2022 International Conference on IC Design and Technology (ICICDT) Pub Date : 2022-09-21 DOI: 10.1109/ICICDT56182.2022.9933104
N. Huy, P. Beckett
{"title":"Optimising Power-Performance in SOI-based Null Convention Logic","authors":"N. Huy, P. Beckett","doi":"10.1109/ICICDT56182.2022.9933104","DOIUrl":"https://doi.org/10.1109/ICICDT56182.2022.9933104","url":null,"abstract":"Null Convention Logic (NCL) is a Quasi Delay-Insensitive (QDI) asynchronous design paradigm in which a control value NULL (i.e., data is not valid) is added to create a symbolically complete and delay insensitive multi-value logic system. As opposed to the centralised clock tree that controls synchronous logic designs, NCL circuits are controlled by (often complex) local completion networks. While this localised handshaking is robust against timing variability, is it not always certain that this asynchronous approach will result in low power. This paper analyses an approach to dynamically optimise the power–delay tradeoffs in the circuit paths using forward body bias (FBB). The results indicate that applying FBB to the P-network in NCL circuits offers a more effective trade-off between performance improvement and power than applying it to the N-network, either alone or together with the P-Network. As only one complex bias voltage generator is required, along with its distribution network and control interfaces, this can be seen to represent a better design choice for NCL systems that exploit FBB.","PeriodicalId":311289,"journal":{"name":"2022 International Conference on IC Design and Technology (ICICDT)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124682708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Tutorial #4 Smart Cut™: Engineered substrate for device performance enhancement 教程#4 Smart Cut™:用于增强器件性能的工程基板
2022 International Conference on IC Design and Technology (ICICDT) Pub Date : 2022-09-21 DOI: 10.1109/icicdt56182.2022.9933073
{"title":"Tutorial #4 Smart Cut™: Engineered substrate for device performance enhancement","authors":"","doi":"10.1109/icicdt56182.2022.9933073","DOIUrl":"https://doi.org/10.1109/icicdt56182.2022.9933073","url":null,"abstract":"","PeriodicalId":311289,"journal":{"name":"2022 International Conference on IC Design and Technology (ICICDT)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124303747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Wide Lock-in Range CDR with Modified DQFD and Coarse-fine Tuning Technique 基于改进DQFD和粗微调技术的宽锁定范围CDR
2022 International Conference on IC Design and Technology (ICICDT) Pub Date : 2022-09-21 DOI: 10.1109/ICICDT56182.2022.9933101
Tzung-Je Lee, Bo-Hao Liao, Chua-Chin Wang
{"title":"Wide Lock-in Range CDR with Modified DQFD and Coarse-fine Tuning Technique","authors":"Tzung-Je Lee, Bo-Hao Liao, Chua-Chin Wang","doi":"10.1109/ICICDT56182.2022.9933101","DOIUrl":"https://doi.org/10.1109/ICICDT56182.2022.9933101","url":null,"abstract":"This paper presents a CDR circuit with wide lock-in range and low jitter. By using the Frequency Increase/Decrease Control circuit and the Modified DQFD (Digital Quadricorrelator Frequency Detector), the lock-in range is enhanced. Besides, the problem of the state loss at wide frequency range detection is avoided. The Coarse-fine Tuning VCO provides two control wires such that separate loop filters could be involved in the dual loops. Thus, the noise and jitter could be further miniaturized. The proposed design is implemented with a typical 40 nm CMOS process. The simulated lock-in range is 1-6.5 GHz and the simulated RMS jitter is 5.79 ps.","PeriodicalId":311289,"journal":{"name":"2022 International Conference on IC Design and Technology (ICICDT)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126448304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
3-Dimensional Integration with High Interconnection Density 具有高互连密度的三维集成
2022 International Conference on IC Design and Technology (ICICDT) Pub Date : 2022-09-21 DOI: 10.1109/ICICDT56182.2022.9933124
Rino Choi, Ye-Eun Hong, Anh-Duy Nguyen
{"title":"3-Dimensional Integration with High Interconnection Density","authors":"Rino Choi, Ye-Eun Hong, Anh-Duy Nguyen","doi":"10.1109/ICICDT56182.2022.9933124","DOIUrl":"https://doi.org/10.1109/ICICDT56182.2022.9933124","url":null,"abstract":"A conventional 2-dimensional scaling down seems to reach its fundamental limits. Further increasing areal integration density required a significant investment of time and money as the dimension of the devices becomes close to those of molecules. On the other hand, the systems that has been requested lately should require more functions to be incorporated in a constrained space. Therefore, 3-dimensional stacking of device layers has attracted attention. To take over 2D scaling of system-on-chip approach, 3D integration should have high density of interconnection density. In this talk, 3D integration for high interconnect density technologies would be addressed. Monolithic 3D is a sequential 3D integration technique to stack multiple device that was proposed to increase integration density and decrease the signal delay and power consumption by reducing interconnection length. Hybrid bonding is a parallel 3D integration technique having a dielectric bond with embedded metal to form interconnections. Higher connectivity can be accomplished because solder bumps on dies are not required to make connections. However, to adopt these technologies, it is necessary to develop novel process techniques and study several technical issues.","PeriodicalId":311289,"journal":{"name":"2022 International Conference on IC Design and Technology (ICICDT)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126541525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
ICICDT 2022 Cover Page ICICDT 2022封面
2022 International Conference on IC Design and Technology (ICICDT) Pub Date : 2022-09-21 DOI: 10.1109/icicdt56182.2022.9933085
{"title":"ICICDT 2022 Cover Page","authors":"","doi":"10.1109/icicdt56182.2022.9933085","DOIUrl":"https://doi.org/10.1109/icicdt56182.2022.9933085","url":null,"abstract":"","PeriodicalId":311289,"journal":{"name":"2022 International Conference on IC Design and Technology (ICICDT)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115817728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
GAQ-SNN: A Genetic Algorithm based Quantization Framework for Deep Spiking Neural Networks GAQ-SNN:一种基于遗传算法的深度峰值神经网络量化框架
2022 International Conference on IC Design and Technology (ICICDT) Pub Date : 2022-09-21 DOI: 10.1109/ICICDT56182.2022.9933070
Duy-Anh Nguyen, Xuan-Tu Tran, F. Iacopi
{"title":"GAQ-SNN: A Genetic Algorithm based Quantization Framework for Deep Spiking Neural Networks","authors":"Duy-Anh Nguyen, Xuan-Tu Tran, F. Iacopi","doi":"10.1109/ICICDT56182.2022.9933070","DOIUrl":"https://doi.org/10.1109/ICICDT56182.2022.9933070","url":null,"abstract":"The usage of Spiking Neural Networks (SNN) for edge-computing has become a major research topic over the years. However, a main challenge still remains, which is the high memory storage requirements of weights for large-scale SNN models. This could be a critical issues as the edge computing platform has tight constraints on the available on-chip memory. To address this issue, we proposed GAQ-SNN, a genetic algorithm based framework to reduce the requirements of memory weights while still maintaining good performance. This is accomplished via two major parts. Firstly, GAQ-SNN will find the optimal neural architecture for the SNN. Secondly, GAQ-SNN find the optimal quantization level for each layer of the SNN. Simulation and hardware implementation results show that, with GAQ-SNN, we could reduce the memory storage up to 12.5× while keeping the accuracy loss to 0.6% when compared to the baseline network.","PeriodicalId":311289,"journal":{"name":"2022 International Conference on IC Design and Technology (ICICDT)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126558597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Invited Talk #21: GaN-on-Si Microwave and mm-Wave Devices 特邀演讲#21:GaN-on-Si微波和毫米波器件
2022 International Conference on IC Design and Technology (ICICDT) Pub Date : 2022-09-21 DOI: 10.1109/icicdt56182.2022.9933097
{"title":"Invited Talk #21: GaN-on-Si Microwave and mm-Wave Devices","authors":"","doi":"10.1109/icicdt56182.2022.9933097","DOIUrl":"https://doi.org/10.1109/icicdt56182.2022.9933097","url":null,"abstract":"","PeriodicalId":311289,"journal":{"name":"2022 International Conference on IC Design and Technology (ICICDT)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126710989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-speed FPGA-based Design and Implementation of Text Search Processor 基于高速fpga的文本搜索处理器的设计与实现
2022 International Conference on IC Design and Technology (ICICDT) Pub Date : 2022-09-21 DOI: 10.1109/ICICDT56182.2022.9933111
Binh Kieu-Do-Nguyen, Tuan-Kiet Dang, Trong-Thuc Hoang, K. Inoue, Toshinori Usugi, M. Odaka, Shuichi Kameyama, C. Pham
{"title":"High-speed FPGA-based Design and Implementation of Text Search Processor","authors":"Binh Kieu-Do-Nguyen, Tuan-Kiet Dang, Trong-Thuc Hoang, K. Inoue, Toshinori Usugi, M. Odaka, Shuichi Kameyama, C. Pham","doi":"10.1109/ICICDT56182.2022.9933111","DOIUrl":"https://doi.org/10.1109/ICICDT56182.2022.9933111","url":null,"abstract":"In the age of computer evolution, the number of data grows swiftly. Moreover, the requirement of extracting the information from the database becomes urgent. Full-text search provides methods to quickly locate multiple keywords inside extensive text data and has gained more consideration in recent years. The proposed tools, such as Lucene, Hyper Estraier, and Namazu, are based on general-purpose processors. They spend more time on index input documents and require more space to store these indexes. In this work, we provide a text search processor design that could perform the full-text search without indexing. The text search processor offers a high-performance, high-level of parallelism and scalability. The design is deployed on Field Programmable Gate Arrays (FPGA) platforms. More than 70K processing units can be integrated on Xilinx Alveo U50. The working frequency achieves 266-MHz after place and route.","PeriodicalId":311289,"journal":{"name":"2022 International Conference on IC Design and Technology (ICICDT)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133437241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Interfacial Layer Engineering to Enhance Noise Immunity of FeFETs for IMC Applications 界面层工程提高效应场效应管在IMC应用中的抗扰性
2022 International Conference on IC Design and Technology (ICICDT) Pub Date : 2022-09-21 DOI: 10.1109/ICICDT56182.2022.9933119
Y. Raffel, Sunanda Thunder, M. Lederer, R. Olivo, R. Hoffmann, L. Pirro, S. Beyer, T. Chohan, Po-Tsang Huang, S. De, T. Kämpfe, K. Seidel, Johannes Heitman
{"title":"Interfacial Layer Engineering to Enhance Noise Immunity of FeFETs for IMC Applications","authors":"Y. Raffel, Sunanda Thunder, M. Lederer, R. Olivo, R. Hoffmann, L. Pirro, S. Beyer, T. Chohan, Po-Tsang Huang, S. De, T. Kämpfe, K. Seidel, Johannes Heitman","doi":"10.1109/ICICDT56182.2022.9933119","DOIUrl":"https://doi.org/10.1109/ICICDT56182.2022.9933119","url":null,"abstract":"This article reports an improvement in the low- frequency noise characteristics in hafnium oxide-based (HfO2) ferroelectric field-effect transistors (FeFET) by interfacial layer (IL) engineering. FeFET devices with silicon dioxide (SiO2) and silicon oxynitride (SiON) as IL were fabricated and characterised. FeFETs with SiON interfaces demonstrated an excellent improvement in variation, and low-frequency noise characteristics. The wider memory window for operation in FeFETs with SiON IL also allows for a higher noise tolerance during the inference operation. Finally, the evaluation of system performance by neuromorphic simulation shows that FeFET with SiON IL are highly immune to noise degradation and endurance, without retention penalty.","PeriodicalId":311289,"journal":{"name":"2022 International Conference on IC Design and Technology (ICICDT)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127952554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Invited Talk #23: 3-levels-stacked InxGa1-xAs Multi-Bridge Channel Field-Effect-Transistors 特邀演讲#23:三电平堆叠InxGa1-xAs多桥通道场效应晶体管
2022 International Conference on IC Design and Technology (ICICDT) Pub Date : 2022-09-21 DOI: 10.1109/icicdt56182.2022.9933121
{"title":"Invited Talk #23: 3-levels-stacked InxGa1-xAs Multi-Bridge Channel Field-Effect-Transistors","authors":"","doi":"10.1109/icicdt56182.2022.9933121","DOIUrl":"https://doi.org/10.1109/icicdt56182.2022.9933121","url":null,"abstract":"","PeriodicalId":311289,"journal":{"name":"2022 International Conference on IC Design and Technology (ICICDT)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121320950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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