Optimising Power-Performance in SOI-based Null Convention Logic

Abstract

Null Convention Logic (NCL) is a Quasi Delay-Insensitive (QDI) asynchronous design paradigm in which a control value NULL (i.e., data is not valid) is added to create a symbolically complete and delay insensitive multi-value logic system. As opposed to the centralised clock tree that controls synchronous logic designs, NCL circuits are controlled by (often complex) local completion networks. While this localised handshaking is robust against timing variability, is it not always certain that this asynchronous approach will result in low power. This paper analyses an approach to dynamically optimise the power–delay tradeoffs in the circuit paths using forward body bias (FBB). The results indicate that applying FBB to the P-network in NCL circuits offers a more effective trade-off between performance improvement and power than applying it to the N-network, either alone or together with the P-Network. As only one complex bias voltage generator is required, along with its distribution network and control interfaces, this can be seen to represent a better design choice for NCL systems that exploit FBB.