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2007 14th International Conference on Mixed Design of Integrated Circuits and Systems最新文献

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A Coloured PETRI Net Based Solution for the Generalized Railway Crossing Problem 基于彩色PETRI网的广义铁路道口问题求解方法
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286245
M. Piotrowicz, K. Slusarczyk, A. Napieralski
{"title":"A Coloured PETRI Net Based Solution for the Generalized Railway Crossing Problem","authors":"M. Piotrowicz, K. Slusarczyk, A. Napieralski","doi":"10.1109/MIXDES.2007.4286245","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286245","url":null,"abstract":"The generalized railway crossing problem was defined as a benchmark problem for comparing different formal methods and methodologies developed for specifying and analysing mixed hardware/software systems. Various solutions of this problem were developed by the real-time researchers. The authors of this paper presents the model of a crossing controller specified in terms of coloured Petri nets. Important technical requirements of the controller are defined by means of temporal logics formulas. The problem had to be slightly redefined to omit the usage of time in the Petri net based model. Safety and liveness properties were verified during the design process. Such an attempt should shorten the design phase and could be a very efficient tool for co-verification of the integrated design methodology.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115679644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Distributed Arithmetic Based Implementation of Fourier Transform Targeted at FPGA Architectures 面向FPGA体系结构的傅里叶变换分布式算法实现
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286139
M. Rawski, M. Wojtynski, T. Wojciechowski, P. Majkowski
{"title":"Distributed Arithmetic Based Implementation of Fourier Transform Targeted at FPGA Architectures","authors":"M. Rawski, M. Wojtynski, T. Wojciechowski, P. Majkowski","doi":"10.1109/MIXDES.2007.4286139","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286139","url":null,"abstract":"Discrete Fourier transform is recognized as one of the basic digital signal processing operations. One of the most efficient methods of performing this transformation is fast Fourier transform (FFT). It has been showed that no algorithm for computing the DFT could have a smaller complexity than the FFT. Thus most FPGA implementations are based on this approach. With the introduction of specialized DSP blocks embedded into programmable architectures the efficiency of FFT is limited by the speed of hardware multipliers of DSP modules. However, programmable architectures provide possibility to increase the performance of digital system by exploitation of parallelisms of implemented algorithms. In this paper application of distributed arithmetic concept to DFT implementation is described. Results showing the performance improvement in comparison to FFT implementation is shown.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123875921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Log-Domain Linear SVM Classifier 对数域线性SVM分类器
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286172
L. Festila, R. Groza, M. Cirlugea, A. Fazakas
{"title":"Log-Domain Linear SVM Classifier","authors":"L. Festila, R. Groza, M. Cirlugea, A. Fazakas","doi":"10.1109/MIXDES.2007.4286172","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286172","url":null,"abstract":"We develop in this paper support vector machine (SVM) parallel classifier for image classifications. The SVM classifier basic modules are new modular log-domain four-quadrant current multipliers. The circuit was simulated taking into account real parameters of transistors in BiCMOS technology. There are many advantages of using such modular log-domain structures in high frequency large dimension circuits and designs.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"57 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126232670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reconfigurable FPGA-Based Hardware Accelerator for Embedded DSP 嵌入式DSP可重构fpga硬件加速器
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286138
G. Rubin, M. Omieljanowicz, A. Petrovsky
{"title":"Reconfigurable FPGA-Based Hardware Accelerator for Embedded DSP","authors":"G. Rubin, M. Omieljanowicz, A. Petrovsky","doi":"10.1109/MIXDES.2007.4286138","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286138","url":null,"abstract":"This paper presents reconfigurable FPGA-based hardware accelerator for embedded DSP. At first the principle of shared-memory based processor are shown and then specific universal balanced architecture is proposed. An example of processor for TVDFT on the given accelerator is also given. Implementation of multiplier and adder based on the serial arithmetic are included as processor elements.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116785679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
JWay - Model-Driven J2EE Application Framework 模型驱动的J2EE应用程序框架
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286254
B. Sakowicz, J. Murlewski, A. Labus, A. Napieralski
{"title":"JWay - Model-Driven J2EE Application Framework","authors":"B. Sakowicz, J. Murlewski, A. Labus, A. Napieralski","doi":"10.1109/MIXDES.2007.4286254","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286254","url":null,"abstract":"Article presents concepts of Web application framework, based on model-driven approach, with high usage of code generation tools and application layout templates. It describes framework's architecture, and typical development lifecycle when it's used. Developed solution bases on open source libraries and frameworks such as Hibernate, Spring, Web Work and XDoclet. Due to implemented ready-to-use modules and model-driven architecture the framework allows for speeding-up development of internet applications and helps with continuous integration process.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116889908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Low-Power Strategy for Delta-Sigma Modulators Delta-Sigma调制器的低功耗策略
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286151
S. Pesenti, P. Clément, D. Stefanovic, M. Kayal
{"title":"A Low-Power Strategy for Delta-Sigma Modulators","authors":"S. Pesenti, P. Clément, D. Stefanovic, M. Kayal","doi":"10.1109/MIXDES.2007.4286151","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286151","url":null,"abstract":"This paper presents a hybrid continuous-discrete-time delta-sigma modulator for portable communication systems following a low-power strategy. The proposed design methodology is extendable to different specifications. A multi-bit technique has been introduced in an efficient manner to optimize the power consumption, and an adaptive algorithm is used to allow for a 3-fold reduction in the number of comparators.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121752718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Low-Noise Current Preamplifier in 120NM CMOS Technology 基于120NM CMOS技术的低噪声电流前置放大器
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286150
H. Uhrmann, H. Zimmermann
{"title":"A Low-Noise Current Preamplifier in 120NM CMOS Technology","authors":"H. Uhrmann, H. Zimmermann","doi":"10.1109/MIXDES.2007.4286150","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286150","url":null,"abstract":"In this paper we discuss the influence of deep-sub-micron CMOS technology on analog circuit design with a special focus on the noise performance and the ability to design low-noise preamplifiers. To point out, why CMOS technology can grow to a key technology in low-noise and high-speed applications, various amplifier stages applied in literature are compared. One, that fits as a current preamplifier for low-noise applications, is the current mirror. Starting from the basic current mirror, an enhanced current preamplifier is developed, that offers low-noise and high-speed operation. The suggested chip is realized in 0.12mum CMOS technology and needs a chip area of 100mum x 280mum. It consumes about l2.1mW at a supply voltage of 1.5V. The presented current preamplifier has a bandwidth of 800MHz and a gain of 44dB. The fields of application for current preamplifiers are, for instance, charge amplifiers, amplifiers for low-voltage differential signaling (LVDS) based point-to-point data links or preamplifiers for photodetectors.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124033150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
System Level Optimization of Static Power Consumption in Nano-CMOS Circuits 纳米cmos电路静态功耗的系统级优化
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286143
D. Helms
{"title":"System Level Optimization of Static Power Consumption in Nano-CMOS Circuits","authors":"D. Helms","doi":"10.1109/MIXDES.2007.4286143","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286143","url":null,"abstract":"Recent design techniques reducing leakage currents at all levels of abstraction are presented. Leakage reduction techniques can be divided by their applicability and the abstraction level into 3 main classes [1]: improved devices, trade off techniques, and leakage management. This work will detail on each of these classes.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126867193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Thermal Imaging of Actively Cooled High-Power Laser Bars 主动冷却高功率激光棒的热成像
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286191
A. Kozłowska, M. Ziegler, J. Tomm, R. Sarzała, W. Nakwaski
{"title":"Thermal Imaging of Actively Cooled High-Power Laser Bars","authors":"A. Kozłowska, M. Ziegler, J. Tomm, R. Sarzała, W. Nakwaski","doi":"10.1109/MIXDES.2007.4286191","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286191","url":null,"abstract":"The results of thermal characterization of actively cooled high-power laser bars are presented. The experimental data obtained by thermal imaging is compared with modelling of temperature distributions in the packaged device. The temperature differences between the central part and the edges of the array are determined. Moreover, we present the microscopic scale temperature profiles in-junction plane and perpendicularly to junction. The thermal behaviour of the bar during long-pulse operation is analyzed both experimentally and theoretically. Possible impact of the thermal properties on the emission characteristics of the bar is discussed.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130181227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Modeling and Co-Simulation of Integrated Microand Nanosystems 集成微纳系统的建模与联合仿真
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286200
P. Janus, T. Bieniek, A. Kociubiński, P. Grabiec, G. Schropfer
{"title":"Modeling and Co-Simulation of Integrated Microand Nanosystems","authors":"P. Janus, T. Bieniek, A. Kociubiński, P. Grabiec, G. Schropfer","doi":"10.1109/MIXDES.2007.4286200","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286200","url":null,"abstract":"In this paper we present a system-level, top-down design/modeling methods for microsystem (MEMS) devices. We describe advanced process co-simulation/emulation of MEMS and integrated circuits. The methodology of hardware-in-the-loop basing on co-simulation of MEMS and IC using signal flow simulators is also discussed.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134211727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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