Thirty-Sixth Southeastern Symposium on System Theory, 2004. Proceedings of the最新文献_第5页

Development and first-phase experimental prototype validation of a single-chip hybrid and reconfigurable multiprocessor signal processor system 单片混合可重构多处理器信号处理系统的开发和第一阶段实验样机验证

Thirty-Sixth Southeastern Symposium on System Theory, 2004. Proceedings of the Pub Date : 2004-09-27 DOI: 10.1109/SSST.2004.1295692

Xiaohui Zhao, J. Heath, P. Maxwell, A. Tan, C. Fernando

{"title":"Development and first-phase experimental prototype validation of a single-chip hybrid and reconfigurable multiprocessor signal processor system","authors":"Xiaohui Zhao, J. Heath, P. Maxwell, A. Tan, C. Fernando","doi":"10.1109/SSST.2004.1295692","DOIUrl":"https://doi.org/10.1109/SSST.2004.1295692","url":null,"abstract":"A previously proposed parallel and scalable hybrid data/command driven architecture (HDCA) was dynamic/reconfigurable at defined \"application\" and \"node\" levels only and was to be implemented with multiple chips. The HDCA is now being developed and experimentally verified as a versatile high performance fault tolerant single-chip multiprocessor computer system-on-chip (SoC) that can execute a wide range of real-time and/or non-real-time signal processing and other applications. It is now being developed to be dynamic/reconfigurable at three levels: the \"application\", \"node\", and \"processor architecture\" levels. A three-phase final prototype development process is being utilized for a complete HDCA SoC. Each phase includes addition and validation of functionality to allow the architecture to be fully dynamic/reconfigurable, in sequence, at the application, node, and processor architecture levels. Experimental hardware prototype testing results are shown for a first-phase prototype of the HDCA. Experimental hardware prototype testing results illustrate that the single-chip first-phase HDCA prototype is able to achieve its functional goal of being able to correctly execute, in a parallel manner, applications described by process flow graphs of different topologies using a heterogeneous mix of processors.","PeriodicalId":309617,"journal":{"name":"Thirty-Sixth Southeastern Symposium on System Theory, 2004. Proceedings of the","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116600436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Input band-pass limiting in a PLL: its influence on interference-induced bifurcation 锁相环的输入带通限制:其对干扰诱导分叉的影响

Thirty-Sixth Southeastern Symposium on System Theory, 2004. Proceedings of the Pub Date : 2004-09-27 DOI: 10.1109/SSST.2004.1295674

J. Stensby, M. Tillman

{"title":"Input band-pass limiting in a PLL: its influence on interference-induced bifurcation","authors":"J. Stensby, M. Tillman","doi":"10.1109/SSST.2004.1295674","DOIUrl":"https://doi.org/10.1109/SSST.2004.1295674","url":null,"abstract":"The sum of a desired tone and an interfering, offset in frequency by v radians/second, tone is considered as the input reference signal for a system comprised of an ideal band-pass limiter and first-order PLL combination. Parameter y denotes the ratio of interfering signal to desired signal amplitudes. In the first of two cases, this two-tone reference signal is supplied directly to the PLL. In the second case, the two-tone reference is band-pass limited before application to the loop. In both cases, if ratio y is sufficiently small (i.e., the interference is relatively weak), the PLL can phase lock to the desired tone, and the interfering tone causes a closed-loop, (2/spl pi//v)-periodic phase error (i.e., a periodic beat note within the loop). However, as y increases, a point y = y/sub b/ is reached where the periodic phase error bifurcates (y/sub b/ is the bifurcation point), and the PLL breaks phase lock. A metric of interference rejection ability, the value y/sub b/, is a function of tone frequency spacing v, PLL closed loop bandwidth G, loop detuning w/spl Delta/ and whether or not input band-pass limiting is employed. Two different algorithms are described for calculating the bifurcation point y/sub b/. The first is based on a numerical solution of the equation that describes the PLL; the second is based on harmonic balance methods. These two algorithms are used to show that, depending on the value of v relative to the PLL closed-loop bandwidth G, input band-pass limiting may, or may not, increase the bifurcation point y/sub b/. Specifically, for detuning w/spl Delta/ = 0, input band-pass limiting decreases the bifurcation point y/sub b/ for a range of v within the PLL closed-loop bandwidth.","PeriodicalId":309617,"journal":{"name":"Thirty-Sixth Southeastern Symposium on System Theory, 2004. Proceedings of the","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121099965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A variable frequency oscillator using modern current feedback amplifiers (CFAs) for high frequency applications 一种采用现代电流反馈放大器(CFAs)的高频振荡器

Thirty-Sixth Southeastern Symposium on System Theory, 2004. Proceedings of the Pub Date : 2004-09-27 DOI: 10.1109/SSST.2004.1295691

S. Natarajan

引用次数: 1

Analysis of fuel cell based power systems using EMTDC electrical power simulator 基于EMTDC电力模拟器的燃料电池动力系统分析

Thirty-Sixth Southeastern Symposium on System Theory, 2004. Proceedings of the Pub Date : 2004-09-27 DOI: 10.1109/SSST.2004.1295662

N. Brooks, T. Baldwin, T. Brinson, J. Ordonez, C. Luongo

引用次数: 9

Quantization of Fano metrics using relative entropy in modeling channels with memory 利用相对熵在有内存信道建模中量化Fano指标

Thirty-Sixth Southeastern Symposium on System Theory, 2004. Proceedings of the Pub Date : 2004-09-27 DOI: 10.1109/SSST.2004.1295672

W. D. Pan

引用次数: 0

Dynamic simulation of a linear variable reluctance motor using coupled network models 基于耦合网络模型的线性变磁阻电机动态仿真

Thirty-Sixth Southeastern Symposium on System Theory, 2004. Proceedings of the Pub Date : 2004-09-27 DOI: 10.1109/SSST.2004.1295640

N. Chayopitak, D.G. Taylor

引用次数: 8

A bang-bang, disturbance rejection algorithm for double integrator systems 双积分器系统的扰动抑制算法

Thirty-Sixth Southeastern Symposium on System Theory, 2004. Proceedings of the Pub Date : 2004-09-27 DOI: 10.1109/SSST.2004.1295624

Jr. R.T. O'Brien

引用次数: 2

Use of surface reconstruction for machine vision 使用表面重建的机器视觉

Thirty-Sixth Southeastern Symposium on System Theory, 2004. Proceedings of the Pub Date : 2004-09-27 DOI: 10.1109/SSST.2004.1295609

R. Munasinghe, C.G. Fernando

引用次数: 1

An optimal measure for camera focus and exposure 相机对焦和曝光的最佳测量

Thirty-Sixth Southeastern Symposium on System Theory, 2004. Proceedings of the Pub Date : 2004-09-27 DOI: 10.1109/SSST.2004.1295702

M. Shirvaikar

引用次数: 85

Real time modeling and control of circulating fluidized bed 循环流化床的实时建模与控制

Thirty-Sixth Southeastern Symposium on System Theory, 2004. Proceedings of the Pub Date : 2004-09-27 DOI: 10.1109/SSST.2004.1295617

S. Valaboju, S. Pulluri, A. Davari, L. Shadle

引用次数: 4