2009 IEEE Workshop on Signal Propagation on Interconnects最新文献

筛选
英文 中文
Measurement and simulation correlation of backplane serdes channel 背板伺服通道的测量与仿真相关
2009 IEEE Workshop on Signal Propagation on Interconnects Pub Date : 2009-05-12 DOI: 10.1109/SPI.2009.5089870
P. Qu
{"title":"Measurement and simulation correlation of backplane serdes channel","authors":"P. Qu","doi":"10.1109/SPI.2009.5089870","DOIUrl":"https://doi.org/10.1109/SPI.2009.5089870","url":null,"abstract":"Serial data link has been widely used in telecom industry. The ability to accurately predict serdes channel insertion loss and return loss plays a critical role in prediction of serdes link performance. In a recent project we designed some test cards with the objective to characterize backplane serdes channel and conduct measurement to simulation correlation. The first part of the study is to try to correlate differential insertion loss (phase and amplitude) of 2D transmission lines between measurement and simulation. A wide band W element model extracted with Simbeor is verified and used in subsequent simulation. In the second part of the study, a full backplane serdes channel consists of daughter cards, backplane, connectors, vias, SMA launches is simulated and compared with TDR measurement. Each element is represented by a S parameter black box and cascaded together with verified W element model for PCB trace. Care must be taken when dealing with cascaded S parameter boxes in time domain simulation. Reasonable agreement is achieved on TDR/TDT signature, differential insertion loss and return loss. The final verification is an eye diagram simulation using real serdes device silicon model and compare eye diagram simulation based on measured s4p and that from S parameter model. In this paper, we presented the methodology and flow that was adopted in this study.","PeriodicalId":309546,"journal":{"name":"2009 IEEE Workshop on Signal Propagation on Interconnects","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124346489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On the construction of uniformly stable multivariate interconnect macromodels 一致稳定多元互联宏观模型的构造
2009 IEEE Workshop on Signal Propagation on Interconnects Pub Date : 2009-05-12 DOI: 10.1109/SPI.2009.5089856
P. Triverio, S. Grivet-Talocia, M. Nakhla
{"title":"On the construction of uniformly stable multivariate interconnect macromodels","authors":"P. Triverio, S. Grivet-Talocia, M. Nakhla","doi":"10.1109/SPI.2009.5089856","DOIUrl":"https://doi.org/10.1109/SPI.2009.5089856","url":null,"abstract":"The generalization of linear macromodeling methods to the multivariate case is considered. The general objective is the extraction of a SPICE-compatible equivalent circuit, which represents with good accuracy the external port behavior of the structure of interest both as a function of frequency and one or more design variables, such as geometry and material parameters. We review the state of the art, and we suggest a new model representation based on a mixed rational/piecewise linear interpolation scheme, which allows the deployment of a simple procedure for checking the global stability of the model within the parameter range of interest. The theory is applied to a significant test case.","PeriodicalId":309546,"journal":{"name":"2009 IEEE Workshop on Signal Propagation on Interconnects","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127897396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Experimental validation of the RC-interconnect effect equalization with negative group delay active circuit in planar hybrid technology 平面混合技术中负群延迟有源电路rc互连效应均衡的实验验证
2009 IEEE Workshop on Signal Propagation on Interconnects Pub Date : 2009-05-12 DOI: 10.1109/SPI.2009.5089836
B. Ravelo, A. Pérennec, M. Le Roy
{"title":"Experimental validation of the RC-interconnect effect equalization with negative group delay active circuit in planar hybrid technology","authors":"B. Ravelo, A. Pérennec, M. Le Roy","doi":"10.1109/SPI.2009.5089836","DOIUrl":"https://doi.org/10.1109/SPI.2009.5089836","url":null,"abstract":"This paper deals with the experimental validation of equalization technique of RC-line degradations based on a negative group delay (NGD) active circuit. The feasibility of this method is illustrated by brief theoretical recalls. Formulas permitting the synthesis of this NGD circuit according to the RC-line parameters are proposed. Then, the analytical predictions are verified by experimental results, which also provide evidence the efficacy of the technique for prototypes in planar hybrid technology. So, for an input square-wave pulse of 25 Msym/s-rate, the rise-time and the propagation delay of the regarded RC-circuit were respectively reduced by 71.4% and 86.4%. As expected, the recovered measured signal shows enhancement of both the raising and trailing edges. Finally, the main benefits provided by this technique compared to the use of repeater are discussed.","PeriodicalId":309546,"journal":{"name":"2009 IEEE Workshop on Signal Propagation on Interconnects","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127396233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Signal integrity of femtosecond pulses patterns in a 500Gb/s all-optical demultiplexer for otdm interconnections by using nonlinearities in semiconductor optical amplifiers 利用半导体光放大器的非线性分析飞秒脉冲模式在500Gb/s otdm全光解复用器中的信号完整性
2009 IEEE Workshop on Signal Propagation on Interconnects Pub Date : 2009-05-12 DOI: 10.1109/SPI.2009.5089844
C. Crognale, A. Di Giansante
{"title":"Signal integrity of femtosecond pulses patterns in a 500Gb/s all-optical demultiplexer for otdm interconnections by using nonlinearities in semiconductor optical amplifiers","authors":"C. Crognale, A. Di Giansante","doi":"10.1109/SPI.2009.5089844","DOIUrl":"https://doi.org/10.1109/SPI.2009.5089844","url":null,"abstract":"This paper numerically investigates the problematic of preserving the signal integrity in a board equipped with Semiconductor Optical Amplifiers (SOAs), optically interconnected to perform optical signal demultiplexing at several hundreds of Gb/s. First, the extreme features of the nonlinear optical gain saturation dynamics in SOAs inputted with dense femtosecond optical pulses signals have been derived by means of a proper theoretical model, suitable for calculating - in a self-consistent way - the quasi-Fermi levels and the carriers temperatures from the instantaneous values of the carrier density and the energy densities in both valence and conduction bands. Then, the results obtained have been used to investigate the potential performances of an interferometric SOA-based pump-probe scheme working as an all-optical ultrafast demultiplexing structure. Simulations have revealed how, with a proper management of the SOAs nonlinear optical gain dynamics, this architecture could extract any 100Gb/s channel from a 500Gb/s pattern, with a high value of its extinction ratio, a negligible amount of optical losses, and no degradation due to the SOA optical gain pattern dependence.","PeriodicalId":309546,"journal":{"name":"2009 IEEE Workshop on Signal Propagation on Interconnects","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125761030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Integral power net integrity analysis of a packaged u-Controller system including the u-Controller on-chip power net distribution 包含u-Controller片上电网分配的盒装u-Controller系统整体电网完整性分析
2009 IEEE Workshop on Signal Propagation on Interconnects Pub Date : 2009-05-12 DOI: 10.1109/SPI.2009.5089866
E. Miersch, M. Goekcen, T. Steinecke
{"title":"Integral power net integrity analysis of a packaged u-Controller system including the u-Controller on-chip power net distribution","authors":"E. Miersch, M. Goekcen, T. Steinecke","doi":"10.1109/SPI.2009.5089866","DOIUrl":"https://doi.org/10.1109/SPI.2009.5089866","url":null,"abstract":"In this paper an application of Integral Analysis Techniques is demonstrated for determining the effect of large simultaneously switching IC Circuit Groups (internal IC-Circuits and I/O's ) on their Power Integrity (PI) and I/O-Signal Integrity (I/O-SI) behavior. The analysis includes the complex Packaging (CP+PCB). A large u-Controller and its wire-bonded Chip-Package(CP) plus its Test-PCB have been used for our study, which is in this paper focused on the analysis of Conducted Power Emission Noise in Frequency- and Time-Domain (FD, TD). The FD-power analysis results are shown in comparison with related Spectrum Analyzer measurements. The methodology can analogously be applied to conducted I/O Signal Noise. The achieved short CPU run times and the ease-of- use are underlined.","PeriodicalId":309546,"journal":{"name":"2009 IEEE Workshop on Signal Propagation on Interconnects","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133945907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Black-box identification of delay-based macromodels from measured terminal responses 从实测终端响应中识别基于延迟的宏模型
2009 IEEE Workshop on Signal Propagation on Interconnects Pub Date : 2009-05-12 DOI: 10.1109/SPI.2009.5089846
P. Triverio, S. Grivet-Talocia, A. Chinea
{"title":"Black-box identification of delay-based macromodels from measured terminal responses","authors":"P. Triverio, S. Grivet-Talocia, A. Chinea","doi":"10.1109/SPI.2009.5089846","DOIUrl":"https://doi.org/10.1109/SPI.2009.5089846","url":null,"abstract":"This paper proposes a new formulation of black-box macromodels for electrically-long scalar interconnects, together with an efficient numerical identification scheme and an optimized SPICE synthesis. The proposed methodology explicitly preserves in the macromodel structure the infinite reflections due to termination mismatch, thus allowing for compact and low-complexity equivalent circuits. Numerical examples show the excellent performance of the proposed technique.","PeriodicalId":309546,"journal":{"name":"2009 IEEE Workshop on Signal Propagation on Interconnects","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131562671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Differential to common mode conversion due to asymmetric ground via configurations 差分到共模转换,由于不对称的地通孔配置
2009 IEEE Workshop on Signal Propagation on Interconnects Pub Date : 2009-05-12 DOI: 10.1109/SPI.2009.5089852
R. Rímolo-Donadío, X. Duan, H. Bruns, C. Schuster
{"title":"Differential to common mode conversion due to asymmetric ground via configurations","authors":"R. Rímolo-Donadío, X. Duan, H. Bruns, C. Schuster","doi":"10.1109/SPI.2009.5089852","DOIUrl":"https://doi.org/10.1109/SPI.2009.5089852","url":null,"abstract":"In this paper, the mode conversion in differential links of printed circuit boards and package structures is investigated, taking into account the ground via arrangement and trace length mismatch. The links are modeled using physics-based via and trace models that have been validated previously with full-wave methods and measurements. The very good numerical efficiency of these models allows simulations of different scenarios in minutes rather than hours compared to full-wave tools. It is shown that an asymmetric ground via configuration in the vicinity of a link end can increase the mode conversion in a comparable proportion to the trace length mismatch. The possibility to mitigate the mode conversion by compensating the trace length mismatch with asymmetric ground via configurations and vice versa is also discussed.","PeriodicalId":309546,"journal":{"name":"2009 IEEE Workshop on Signal Propagation on Interconnects","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123663945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Equivalent victim model of the coupled interconnects for simulating crosstalk induced glitches and delays 用于模拟串扰引起的故障和延迟的耦合互连等效受害模型
2009 IEEE Workshop on Signal Propagation on Interconnects Pub Date : 2009-05-12 DOI: 10.1109/SPI.2009.5089850
S. Hasan, A. K. Palit, W. Anheier
{"title":"Equivalent victim model of the coupled interconnects for simulating crosstalk induced glitches and delays","authors":"S. Hasan, A. K. Palit, W. Anheier","doi":"10.1109/SPI.2009.5089850","DOIUrl":"https://doi.org/10.1109/SPI.2009.5089850","url":null,"abstract":"Noise effects due to parasitic couplings between two closely located neighboring wires have significant impact on the performance of the DSM chips. Analysis of a single wire with all its couplings is required to find out the maximum effect of the crosstalk noise both in terms of glitch and delay. This paper introduces a decoupled RLGC transient model for victim wire which is highly accurate and flexible. This model can be used to compute the maximum delay and glitch effect due to crosstalk on a victim wire under different slew rates and delays of aggressor and victim signals. The equivalent victim model's accuracy is validated by the PSPICE simulation results and yet the simulation speed is at least 13 times faster than the latter.","PeriodicalId":309546,"journal":{"name":"2009 IEEE Workshop on Signal Propagation on Interconnects","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115527609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Conductor modeling with the surface admittance operator of triangles 用三角形表面导纳算子进行导体建模
2009 IEEE Workshop on Signal Propagation on Interconnects Pub Date : 2009-05-12 DOI: 10.1109/SPI.2009.5089860
T. Demeester, D. De Zutter
{"title":"Conductor modeling with the surface admittance operator of triangles","authors":"T. Demeester, D. De Zutter","doi":"10.1109/SPI.2009.5089860","DOIUrl":"https://doi.org/10.1109/SPI.2009.5089860","url":null,"abstract":"This paper presents an accurate solution for the discretization of the Dirichlet-to-Neumann (DtN) operator in triangles. The resulting DtN matrix can be used for modeling conductors that are composed of triangles with a finite conductivity, and guarantees an accurate solution up to frequencies at which the skin effect is strongly present. The method is illustrated with some numerical examples.","PeriodicalId":309546,"journal":{"name":"2009 IEEE Workshop on Signal Propagation on Interconnects","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116113409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Polarization mode basis functions for modeling insulator-coated through-silicon via (TSV) interconnections 模拟绝缘子涂层硅通孔(TSV)互连的极化模式基函数
2009 IEEE Workshop on Signal Propagation on Interconnects Pub Date : 2009-05-12 DOI: 10.1109/SPI.2009.5089849
K. Han, M. Swaminathan
{"title":"Polarization mode basis functions for modeling insulator-coated through-silicon via (TSV) interconnections","authors":"K. Han, M. Swaminathan","doi":"10.1109/SPI.2009.5089849","DOIUrl":"https://doi.org/10.1109/SPI.2009.5089849","url":null,"abstract":"For the design of high-density 3-D integration, this paper presents a method to model through-silicon via (TSV) interconnections. Focusing on the modeling of annular insulator coating around the TSV, this paper proposes a new type of modal basis functions that describe polarization current density distribution in insulator. The equivalent network including modal excess capacitance from the basis functions provides accurate electrical characteristics, compared with analytic and EM simulation results.","PeriodicalId":309546,"journal":{"name":"2009 IEEE Workshop on Signal Propagation on Interconnects","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129595735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信
小红书