C. Bermond, L. Cadix, A. Farcy, T. Lacrevaz, P. Leduc, B. Fléchet
{"title":"High frequency characterization and modeling of high density TSV in 3D integrated circuits","authors":"C. Bermond, L. Cadix, A. Farcy, T. Lacrevaz, P. Leduc, B. Fléchet","doi":"10.1109/SPI.2009.5089840","DOIUrl":"https://doi.org/10.1109/SPI.2009.5089840","url":null,"abstract":"High frequency characterization and modeling of Through Silicon Vias (TSVs) for new 3D chip staking are presented in this paper. Works focus on high density TSVs, up to 106 cm−2, with pitch below 10 µm and aggressive wafer thinning to maintain TSV aspect ratio in a range between 5 and 10. Equivalent electrical RLCG models of TSVs with height of 15 µm and diameter of 3 µm are extracted up to 20 GHz. It is shown that values extracted for components are directly related to design and material characteristics used to process 3D TSVs.","PeriodicalId":309546,"journal":{"name":"2009 IEEE Workshop on Signal Propagation on Interconnects","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132610176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Compromised impedance match design for signal integrity of pogo pins structures with different signal-ground patterns","authors":"Ruey-Bo Sun, R. Wu, Shih-Wei Hsiao","doi":"10.1109/SPI.2009.5089838","DOIUrl":"https://doi.org/10.1109/SPI.2009.5089838","url":null,"abstract":"This paper proposes a systematic methodology to model the single-ended and differential pogo pin structures for the analysis of signal integrity (SI), especially the reflected noise. A measurement method is developed for de-embedding the specialized fixture in the characterization of the pogo pins. The simulation and modeling methodologies are verified by the favorable comparison with the measured results from DC to 10GHz. Finally, an applicable range of impedance for satisfying the desired specifications of return loss is derived. By a design chart of the impedance versus the pogo pin geometry, the compromised impedance design charts for small reflection in different S/G ratios and pin patterns are given.","PeriodicalId":309546,"journal":{"name":"2009 IEEE Workshop on Signal Propagation on Interconnects","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124204246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Achar, M. Nakhla, A. Sridhar, Harjot S. Dhindsa, D. Paul
{"title":"Fast analysis of power distribution networks using waveform relaxation","authors":"R. Achar, M. Nakhla, A. Sridhar, Harjot S. Dhindsa, D. Paul","doi":"10.1109/SPI.2009.5089834","DOIUrl":"https://doi.org/10.1109/SPI.2009.5089834","url":null,"abstract":"This paper presents a fast algorithm for transient simulation of power grids in VLSI systems using waveform relaxation techniques. Novel partitioning methods and convergence accelerators are developed for fast convergence of waveform relaxation iterations when applied to power grid networks. Unlike the direct-solvers, the new method is highly parallelizable and yields significant speed-ups. Numerical examples are presented to demonstrate the validity and efficiency of the proposed method.","PeriodicalId":309546,"journal":{"name":"2009 IEEE Workshop on Signal Propagation on Interconnects","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114604276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Identification of interconnect failure mechanisms using RF impedance analysis","authors":"Daeil Kwon, M. Azarian, M. Pecht","doi":"10.1109/SPI.2009.5089855","DOIUrl":"https://doi.org/10.1109/SPI.2009.5089855","url":null,"abstract":"This paper presents RF impedance analysis as a non-destructive indicator of interconnect failure mechanisms. Physical changes on a printed circuit board can be detected using the TDR reflection coefficient as a measure of RF impedance. The test circuit in this study consisted of an impedance-controlled circuit board, a surface mount low-pass filter, and two solder joints providing both mechanical and electrical connections between them. A cyclic mechanical load was applied to generate either solder pad separation failures or cracking of the solder joints. In the case of pad separation, the test results showed that the TDR reflection coefficient gradually decreased as the pad lifted off the circuit board, which was distinguishable from the TDR response due to solder joint cracking. These results are explained using a simple theoretical analysis of the effect of each failure mechanism on impedance. This demonstrates that RF impedance analysis provides for the determination of failure mechanisms as well as early detection of both pad separation and solder joint degradation. The detection sensitivity for solder joint cracking using this technique is also discussed.","PeriodicalId":309546,"journal":{"name":"2009 IEEE Workshop on Signal Propagation on Interconnects","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130762025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pilsoo Lee, J. Wee, Kyoo-Yeong Lee, Inchae Song, Boo‐Gyoun Kim
{"title":"Analysis of EMI dependence on signal duty and supplied voltage","authors":"Pilsoo Lee, J. Wee, Kyoo-Yeong Lee, Inchae Song, Boo‐Gyoun Kim","doi":"10.1109/SPI.2009.5089869","DOIUrl":"https://doi.org/10.1109/SPI.2009.5089869","url":null,"abstract":"In this paper, we analyzed EMI dependence on signal duty ratio and power supplied voltage. The EMI levels of the chip-mounted modules were tested and the near-field and far-field emission levels were measured at 800 MHz frequency (the 2nd harmonic of the clock). The relation between EMI levels and line spectra of signals was analyzed for chip design quality, especially including clock generation circuitry and data paths. In addition, voltage-scaling operation and slew rate control operation which affect radiated emission levels, were tested to investigate the effect of duty ratio and slew asymmetry on EMI generation.","PeriodicalId":309546,"journal":{"name":"2009 IEEE Workshop on Signal Propagation on Interconnects","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132053199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Andersson, Bjorn Nilsson, J. Pihl, L. Svensson, P. Larsson-Edefors
{"title":"Supply voltage drop study considering on-chip self inductance of a 32-bit processor's power grid","authors":"D. Andersson, Bjorn Nilsson, J. Pihl, L. Svensson, P. Larsson-Edefors","doi":"10.1109/SPI.2009.5089853","DOIUrl":"https://doi.org/10.1109/SPI.2009.5089853","url":null,"abstract":"Conventional IR drop analysis suggests that on-chip inductive effects can be neglected when estimating supply voltage drops. We present a supply voltage drop analysis for a commercial 32-bit application processor. Our power grid model uses a backbone RL extracted netlist of the processor's power grid, complemented with capacitances from the processor design and a current signature defined by the worst-case switching test vector, located in the power-up sequence of the processor. Our circuit simulations show that on-chip self inductance makes the actual supply voltage drop deviate by more than 55% and 25% from the ∼6% and ∼8% drop, respectively, of nominal supply voltage that a conventional IR power grid model yields.","PeriodicalId":309546,"journal":{"name":"2009 IEEE Workshop on Signal Propagation on Interconnects","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132742102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modeling the interconnection of a pseudo-differential link using a wide return conductor","authors":"F. Broydé, E. Clavelier","doi":"10.1109/SPI.2009.5089862","DOIUrl":"https://doi.org/10.1109/SPI.2009.5089862","url":null,"abstract":"A type of pseudo-differential link uses a floating termination circuit connected to an interconnection comprising a return conductor wider than the transmission conductors. For n channels, the link is designed using a per-unit-length (p.u.l.) impedance matrix and a p.u.l admittance matrix, both of size n × n. The paper establishes the relationship between this model and an alternative model which uses a p.u.l. impedance matrix and a p.u.l admittance matrix of size (n+1)×(n+1). In the process, we define two vectors which may be used to assess external crosstalk.","PeriodicalId":309546,"journal":{"name":"2009 IEEE Workshop on Signal Propagation on Interconnects","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127831983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An equivalent circuit model for the identification of the stub resonance due to differential vias on PCB","authors":"V. Ricchiuti, F. de Paulis, A. Orlandi","doi":"10.1109/SPI.2009.5089839","DOIUrl":"https://doi.org/10.1109/SPI.2009.5089839","url":null,"abstract":"The modern telecommunication equipments consist of boards connected by thick backplanes where differential traces on different layers transmit high speed digital signals. These signals switch from different layers by means of plated through holes that, when not used, are stubs introducing dips on the insertion losses of the used traces. The paper presents an algorithm for modeling differential vias connected to differential traces, so to evaluate the resonance frequency due to the stubs connected to the vias.","PeriodicalId":309546,"journal":{"name":"2009 IEEE Workshop on Signal Propagation on Interconnects","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123064294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fast passivity enforcement technique for common-pole S-parameter multiport systems","authors":"D. Deschrijver, T. Dhaene","doi":"10.1109/SPI.2009.5089857","DOIUrl":"https://doi.org/10.1109/SPI.2009.5089857","url":null,"abstract":"This paper applies a reliable and efficient algorithm for passivity enforcement of common-pole multiport S-parameter macromodels. It ensures that the maximum passivity violation decreases monotonically in each iteration step, and convergence to a uniformly passive macromodel is guaranteed.","PeriodicalId":309546,"journal":{"name":"2009 IEEE Workshop on Signal Propagation on Interconnects","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126861895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Vector Fitting vs. Levenberg-Marquardt : Some experiments","authors":"L. Knockaert, F. Ferranti, T. Dhaene","doi":"10.1109/SPI.2009.5089858","DOIUrl":"https://doi.org/10.1109/SPI.2009.5089858","url":null,"abstract":"A discussion and evaluation of the Vector Fitting technique is presented, in comparison with a special flavor of the Levenberg-Marquardt method, which is one of the most successful quasi Gauss-Newton techniques. Although generally slower than Vector Fitting, the Levenberg-Marquardt method can achieve greater accuracy than Vector Fitting, because of its unique ability to navigate between local minima.","PeriodicalId":309546,"journal":{"name":"2009 IEEE Workshop on Signal Propagation on Interconnects","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124403785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}