2015 IEEE International Circuits and Systems Symposium (ICSyS)最新文献

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Sub-picosecond jitter resolution wide range digital delay line for SoC integration 用于SoC集成的亚皮秒抖动分辨率宽范围数字延迟线
2015 IEEE International Circuits and Systems Symposium (ICSyS) Pub Date : 2015-09-01 DOI: 10.1109/CIRCUITSANDSYSTEMS.2015.7394062
Bilal I. Abdulrazzaq, I. Halin, R. Sidek, S. Shafie, N. A. M. Yunus, S. Kawahito
{"title":"Sub-picosecond jitter resolution wide range digital delay line for SoC integration","authors":"Bilal I. Abdulrazzaq, I. Halin, R. Sidek, S. Shafie, N. A. M. Yunus, S. Kawahito","doi":"10.1109/CIRCUITSANDSYSTEMS.2015.7394062","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2015.7394062","url":null,"abstract":"A novel three-stage architecture programmable digital delay line (DDL) with a picosecond resolution, 1μs range, and sub-picosecond jitter performance is proposed. Through circuit simulation, a dynamic range of 1μs is obtained in the first stage using 10-bit counters operating at a frequency of 1 GHz. The second stage further refines the delay to 23ps using a tapped inverter chain architecture. Finally, the third stage constructed using a DLL with NAND gate based delay elements further refines the delay step to 1ps resolution with a 0.1ps RMS jitter performance. The proposed digital delay line is designed using a standard 0.13μm Silterra CMOS technology.","PeriodicalId":306918,"journal":{"name":"2015 IEEE International Circuits and Systems Symposium (ICSyS)","volume":"414 16","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133051779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An improved readout topology of resistive sensor array for reduced measurement error 一种改进的电阻式传感器阵列读出拓扑结构,减小了测量误差
2015 IEEE International Circuits and Systems Symposium (ICSyS) Pub Date : 2015-09-01 DOI: 10.1109/CIRCUITSANDSYSTEMS.2015.7394072
D. N. Talib, S. Shafie, M. Hamidon, F. Ahmad
{"title":"An improved readout topology of resistive sensor array for reduced measurement error","authors":"D. N. Talib, S. Shafie, M. Hamidon, F. Ahmad","doi":"10.1109/CIRCUITSANDSYSTEMS.2015.7394072","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2015.7394072","url":null,"abstract":"Readout circuit integrated with large scale sensors array is important for improving the effectiveness of data acquisition system. However to design such system, it will require a variety of additional components which contributes to the increment of power consumption. In this paper we proposed an improved method of readout topology for resistive sensor array to reduce the measurement error. A new equation is also proposed to obtain the resistance value. A simulation has been done on 8×8 matrix sensor array represented by 64 fixed resistors and 8 standard reference resistors. The results show that the optimum reference resistance is 510 Ω for the value range between 100 Ω and 100 kΩ, and the improved percentage error is kept to be lower than 5%.","PeriodicalId":306918,"journal":{"name":"2015 IEEE International Circuits and Systems Symposium (ICSyS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134117936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A comparison between two different FPGA-based topologies of first order sigma-delta modulator 一阶σ - δ调制器两种不同fpga拓扑的比较
2015 IEEE International Circuits and Systems Symposium (ICSyS) Pub Date : 2015-09-01 DOI: 10.1109/CIRCUITSANDSYSTEMS.2015.7394077
Maral Faghani, M. Isa, M. Hamidon, Amin Mazaheri
{"title":"A comparison between two different FPGA-based topologies of first order sigma-delta modulator","authors":"Maral Faghani, M. Isa, M. Hamidon, Amin Mazaheri","doi":"10.1109/CIRCUITSANDSYSTEMS.2015.7394077","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2015.7394077","url":null,"abstract":"Integrating sigma-delta modulator (SDM) in FPGA causes to have quantization noise inside interested bandwidth. This paper compares and analyzes between two possible FPGA-based SDM structures which are non-noise shaper SDM and noise-shaper SDM. The difference between these two structures is in the integrator block. All other SDM constitutive components are the same for both structures. First-order noise-shaper SDM with its maximum integration for FPGA implementation is reported. The advantages of noise-shaper SDM over non-noise shaper SDM are the elimination of input peak signal error as well as the increment of input voltage range. Moreover, higher suppression in signal harmonics results in better reconstruction of input signal at the output. However, the most important outcome is the improvement of quantization noise shaping out of the interested bandwidth which results higher SNR at the output.","PeriodicalId":306918,"journal":{"name":"2015 IEEE International Circuits and Systems Symposium (ICSyS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123532489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Capacitive sensing system for frying oil assessment during heating 用于煎炸油加热评定的电容式传感系统
2015 IEEE International Circuits and Systems Symposium (ICSyS) Pub Date : 2015-09-01 DOI: 10.1109/CIRCUITSANDSYSTEMS.2015.7394081
A. Y. Khaled, S. Abd Aziz, W. I. Ismail, F. Rokhani
{"title":"Capacitive sensing system for frying oil assessment during heating","authors":"A. Y. Khaled, S. Abd Aziz, W. I. Ismail, F. Rokhani","doi":"10.1109/CIRCUITSANDSYSTEMS.2015.7394081","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2015.7394081","url":null,"abstract":"Thethermal degradation process during frying contributes to the formation of polar compounds in theoil, which in turn changes the oil quality. A capacitive sensing system utilizing interdigitated electrode design was built to assess the frying oil degradation during heating by measuring the changes on its total polar compounds (TPC). In total of 60 samples of 100 ml palm oil were heated at 180° C up to 30 hours using a laboratory oven. For each one hour increment, one sample was taken out of the oven and cooled at room temperature before analysis. The TPC of each heated sample was measured using the custom-built capacitive sensing system and using a commercialized frying oil tester, Testo 270 (InstruMartlnc, Germany). A two tailed independent sample t-test was carried out to test the agreement between both methods. The results showed that there was no significant difference in measured TPC values from both methods (p = 0.983, α = 0.05 and 95% confidence interval). Thus, the results demonstrated significant correlation between the measurements using the capacitive sensing system and the Testo 270. The custom-built capacitive sensing system has good potential for a simple and inexpensive way of monitoring frying oil degradation.","PeriodicalId":306918,"journal":{"name":"2015 IEEE International Circuits and Systems Symposium (ICSyS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130429096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
DSP ASIC module Design for natural frequency of ECG signal 针对心电信号固有频率的DSP ASIC模块设计
2015 IEEE International Circuits and Systems Symposium (ICSyS) Pub Date : 2015-09-01 DOI: 10.1109/CIRCUITSANDSYSTEMS.2015.7394067
N. A. Abdul-Kadir, N. Safri, M. A. Othman
{"title":"DSP ASIC module Design for natural frequency of ECG signal","authors":"N. A. Abdul-Kadir, N. Safri, M. A. Othman","doi":"10.1109/CIRCUITSANDSYSTEMS.2015.7394067","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2015.7394067","url":null,"abstract":"This study implemented software to hardware design for a part of ECG system which is intended to detect and classify atrial fibrillation. The feature extraction process was chosen to be implemented into hardware design. The chosen algorithm was the natural frequency of ECG signal that was obtained from second-order system. Steps taken from digital signal processing to signal processing in hardware on Field-programmable gated-array (FPGA) is discussed. By optimizing resource utilization, the performance was analyzed for 2 hardware designs, Design 1 and Design 2 that needed 34 and 29 resource utilizations, respectively. Results from QuartusII shows Design 2 used less logic utilization than Design 1, i.e. 36 as compared to 2530. Therefore, Design 2 is considered a better design.","PeriodicalId":306918,"journal":{"name":"2015 IEEE International Circuits and Systems Symposium (ICSyS)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122718031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Comparison on TiO2 thin film deposition method for fluidic based glucose memristor sensor 流体型葡萄糖忆阻器传感器中TiO2薄膜沉积方法的比较
2015 IEEE International Circuits and Systems Symposium (ICSyS) Pub Date : 2015-09-01 DOI: 10.1109/CIRCUITSANDSYSTEMS.2015.7394060
N. Hadis, Asrulnizam Abd Manaf, S. H. Herman
{"title":"Comparison on TiO2 thin film deposition method for fluidic based glucose memristor sensor","authors":"N. Hadis, Asrulnizam Abd Manaf, S. H. Herman","doi":"10.1109/CIRCUITSANDSYSTEMS.2015.7394060","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2015.7394060","url":null,"abstract":"This paper studies the behavior of fluidic based memristor sensor in detecting glucose liquid. Two types of memristor sensors were produced using two different deposition methods which were physical vapor deposition (PVD) method and sol-gel spin coating method. The equipment used in doing the PVD was radio frequency (RF) sputtering machine, and normal spin coating machine was employed for the sol-gel deposition. The memristor sensors were then tested with three glucose concentrations in a fluidic based platform. An observation showed that the ROFF/RON ratio of the sol gel spin coating memristor sensor was higher than the PVD memristor sensor. The increment in the concentration of the glucose liquid also raised the ratio for both deposition methods. The sol-gel spin coating deposition recorded an exponential relationship between its ROFF/RON ratio to the glucose concentration while a linear relationship was observed in PVD method for the same parameters. As conclusion, the sol-gel spin coating method has more advantages than the PVD method due to its high sensing capability, shorter deposition time and lower cost.","PeriodicalId":306918,"journal":{"name":"2015 IEEE International Circuits and Systems Symposium (ICSyS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128851369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
An FPGA-based embedded system for portable and cost-efficient bio-sensing: A low-cost controller for biomedical diagnosis 一种基于fpga的嵌入式便携式低成本生物传感系统:一种低成本的生物医学诊断控制器
2015 IEEE International Circuits and Systems Symposium (ICSyS) Pub Date : 2015-09-01 DOI: 10.1109/CIRCUITSANDSYSTEMS.2015.7394053
Ikho Lee, Byungsub Kim, Seung-woo Lee, Ki-Young Lee, H. Yi
{"title":"An FPGA-based embedded system for portable and cost-efficient bio-sensing: A low-cost controller for biomedical diagnosis","authors":"Ikho Lee, Byungsub Kim, Seung-woo Lee, Ki-Young Lee, H. Yi","doi":"10.1109/CIRCUITSANDSYSTEMS.2015.7394053","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2015.7394053","url":null,"abstract":"This paper presents a design of an embedded system for a portable and cost effective bio-sensing. With our system, users can easily and cost-efficiently generate the necessary control signals such as cyclic waves for bio-sensors with precisely controlled timing. The bio-sensing system consists of an analog-to-digital converter (ADC) used for data acquisition, digital-to-analog converter (DAC) in order to generate cyclic wave for a biosensor, field programmable gate array (FPGA) to interface with computer, and potentiostat for biosensor signal processing. Our system has two modes that are software controlled real time mode for real-time data acquisition and hardware controlled burst mode for high-speed data acquisition. The system accuracy was evaluated by series R-test. In cyclic voltammetry test with a Ru(NH3)6Cl3, a graph provided by our system has 2.77% relative error at current peak compared with the data acquired by a 18 times more expensive commercial system.","PeriodicalId":306918,"journal":{"name":"2015 IEEE International Circuits and Systems Symposium (ICSyS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128329930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A multiband 130nm CMOS second order band pass filter for LTE bands 一种用于LTE频段的多频段130nm CMOS二阶带通滤波器
2015 IEEE International Circuits and Systems Symposium (ICSyS) Pub Date : 2015-09-01 DOI: 10.1109/CIRCUITSANDSYSTEMS.2015.7394073
N. Kamsani, Veeraiyah Thangasamy, M. Bukhori, S. Shafie
{"title":"A multiband 130nm CMOS second order band pass filter for LTE bands","authors":"N. Kamsani, Veeraiyah Thangasamy, M. Bukhori, S. Shafie","doi":"10.1109/CIRCUITSANDSYSTEMS.2015.7394073","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2015.7394073","url":null,"abstract":"With increasing consumer demand for wireless devices to support multiple air standards and applications, there have been increased trends for implementation multimode multiband (MMMB) devices in the RF front-end of wireless handsets. This paper presents a design of multiband band pass filter (BPF) in 130nm standard CMOS technology that can operates in 12 different LTE bands (band 1, 2, 3, 4, 5, 8, 9, 11, 18, 19, 21 and 25). The filter response is tuned by employing switched capacitors in parallel with LC resonant circuit; and Q-factor of the filter is tuned using cross-coupled differential pair connected across the resonant circuit. The gain of 30dB with maximum bandwidth of 145 MHz at 900MHz center frequency, 328MHz at 1.5GHz center frequency and 594MHz at 2GHz center frequency is achieved at 3.3V supply. The Q-factor of the filter is tunable through 2.1 to 8.1. The 1-dB compression point (P1dB), third order intercept point (IP3), and noise figure achieved are -39dBm, -25dBm and 3.83dB respectively. The designed filter has the features of less BOM count and smaller area making it suitable for integration in modern wireless applications.","PeriodicalId":306918,"journal":{"name":"2015 IEEE International Circuits and Systems Symposium (ICSyS)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124114936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 2-stage 40 GHz CMOS power amplifier driver for mm-Wave radio-over-fiber applications 用于毫米波光纤无线电应用的2级40 GHz CMOS功率放大器驱动器
2015 IEEE International Circuits and Systems Symposium (ICSyS) Pub Date : 2015-09-01 DOI: 10.1109/CIRCUITSANDSYSTEMS.2015.7394064
N. Farid, S. M. M. Mohd Hassan, R. Sanusi, A. I. Abdul Rahim
{"title":"A 2-stage 40 GHz CMOS power amplifier driver for mm-Wave radio-over-fiber applications","authors":"N. Farid, S. M. M. Mohd Hassan, R. Sanusi, A. I. Abdul Rahim","doi":"10.1109/CIRCUITSANDSYSTEMS.2015.7394064","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2015.7394064","url":null,"abstract":"A 40 GHz power amplifier (PA) driver for the remote antenna unit (RAU) transceiver of a mm-wave radio-over-fiber (RoF) system is presented in this paper. Mm-wave RoF is proposed as a complementary technology to fiber-to-the-home to minimize costs and to increase bandwidth. In order for RoF to be feasible, the cost of the RAU must be minimized through low-cost technology such as CMOS. The PA driver is designed using a 0.13μm RF CMOS process. The architecture used is a 2-stage, double-cascode amplifier. It has input and output reflection coefficients that are better than -10 dB over a bandwidth of 7 GHz. Maximum gain is 25.4 dB and output P1dB is 6.4 dBm. This paper is the first reported use of a two-stage, double-cascode, 130nm CMOS amplifier for the implementation of a 40 GHz radio-over-fiber system.","PeriodicalId":306918,"journal":{"name":"2015 IEEE International Circuits and Systems Symposium (ICSyS)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131742500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
CMOS differential difference voltage follower transconductance amplifier CMOS差分电压从动器跨导放大器
2015 IEEE International Circuits and Systems Symposium (ICSyS) Pub Date : 2015-09-01 DOI: 10.1109/CIRCUITSANDSYSTEMS.2015.7394080
M. Kumngern
{"title":"CMOS differential difference voltage follower transconductance amplifier","authors":"M. Kumngern","doi":"10.1109/CIRCUITSANDSYSTEMS.2015.7394080","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2015.7394080","url":null,"abstract":"This paper presents a new active building block for analog circuit applications called differential difference voltage follower transconductance amplifier. It consists of two parts: first part is the input that provides a differential difference voltage follower and second part is the transconductance amplifier that uses to convert differential difference input voltage to the output current. Hence, the electronic tuning capability of the proposed active building block can be obtained. The active building block is used to realize a universal biquadratic filter as an example application. Simulation results using 0.5 μm standard CMOS process are used to confirm the proposed active building block.","PeriodicalId":306918,"journal":{"name":"2015 IEEE International Circuits and Systems Symposium (ICSyS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130290085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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