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Investigating the impact of on-chip interconnection noise on Dynamic Thermal Management efficiency 研究片上互连噪声对动态热管理效率的影响
2015 IEEE International Circuits and Systems Symposium (ICSyS) Pub Date : 2015-09-10 DOI: 10.1109/PRIME.2015.7251348
Somayeh Rahimipour, W. N. Flayyih, N. Kamsani, M. Stan, Fakhrul Zaman Rohani
{"title":"Investigating the impact of on-chip interconnection noise on Dynamic Thermal Management efficiency","authors":"Somayeh Rahimipour, W. N. Flayyih, N. Kamsani, M. Stan, Fakhrul Zaman Rohani","doi":"10.1109/PRIME.2015.7251348","DOIUrl":"https://doi.org/10.1109/PRIME.2015.7251348","url":null,"abstract":"Dynamic Thermal Management (DTM) emerged as a solution to address the reliability challenges with thermal hotspots and unbalanced temperatures. DTM efficiency is highly affected by the accuracy of the temperature information presented to the DTM manager. This work aims to investigate the effect of inaccuracy caused by the deep sub-micron (DSM) noise during the transmission of temperature information to the manager on DTM efficiency. A simulation framework has been developed and results show up to 38% DTM performance degradation and 18% unattended cycles in emergency temperature under DSM noise. The finding highlights the importance of further research in providing reliable on-chip data transmission in DTM application.","PeriodicalId":306918,"journal":{"name":"2015 IEEE International Circuits and Systems Symposium (ICSyS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117039855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Modeling and analysis of DLLs for locking and jitter based on Simulink 基于Simulink的锁与抖动dll建模与分析
2015 IEEE International Circuits and Systems Symposium (ICSyS) Pub Date : 2015-09-01 DOI: 10.1109/CIRCUITSANDSYSTEMS.2015.7394083
Chen Yang, Li Wenyuan
{"title":"Modeling and analysis of DLLs for locking and jitter based on Simulink","authors":"Chen Yang, Li Wenyuan","doi":"10.1109/CIRCUITSANDSYSTEMS.2015.7394083","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2015.7394083","url":null,"abstract":"This paper presents a behavioral modeling and simulation for delay-locked loops (DLLs) based on MATLAB Simulink. The fast locking time and output jitter performance of DLLs are analyzed in the model. Through systematical simulation in MATLAB Simulink, it can be achieved that the locking time is determined by current of Charge pump and filter capacitor. This paper introduces the equations related to output jitter from noise sources (input reference clock, phase frequency detector, charge pump and voltage-controlled delay line) for stage numbers, loop bandwidth, noise intensity and reset time. Furthermore the model is applied to verify these equations for analyzing output jitter and provides the design considerations for optimizing circuit performance.","PeriodicalId":306918,"journal":{"name":"2015 IEEE International Circuits and Systems Symposium (ICSyS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125391313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Asymmetric T-coil, resistive feedback cascode low noise amplifier for ultrawideband receiver 用于超宽带接收机的非对称t圈电阻反馈级联低噪声放大器
2015 IEEE International Circuits and Systems Symposium (ICSyS) Pub Date : 2015-09-01 DOI: 10.1109/CIRCUITSANDSYSTEMS.2015.7394055
Siti Noor Idora Syafinaz Zulkepli, T. Zulkifli
{"title":"Asymmetric T-coil, resistive feedback cascode low noise amplifier for ultrawideband receiver","authors":"Siti Noor Idora Syafinaz Zulkepli, T. Zulkifli","doi":"10.1109/CIRCUITSANDSYSTEMS.2015.7394055","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2015.7394055","url":null,"abstract":"This paper presents a wideband low-noise amplifier (LNA) using 0.18-μm CMOS process which is combination of resistive feedback and T-coil techniques. The cascode stage with a resistive feedback technique to ensure the stability of the amplifier is proposed. The T-coil topology is adopted to achieve wideband output response that improves the bandwidth extension of the CMOS differential amplifier. The proposed topology exhibits a bandwidth of 3.1-7.0 GHz, a power gain of 12 dB, a minimum noise figure of 4.00 dB while drawing 1.4 mW from 1.8 V power supply. The simulated IIP3 of the amplifier is -9.5 dBm at 5.5 GHz. Hence, the T-coil network and cascode topology with resistive feedback can be implemented for mode 1, UWB standard.","PeriodicalId":306918,"journal":{"name":"2015 IEEE International Circuits and Systems Symposium (ICSyS)","volume":"53 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116841512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Neural network-based non-linear A/D conversion 基于神经网络的非线性A/D转换
2015 IEEE International Circuits and Systems Symposium (ICSyS) Pub Date : 2015-09-01 DOI: 10.1109/CIRCUITSANDSYSTEMS.2015.7394082
M. Bensenouci, H. Escid, M. Attari, A. Bensenouci
{"title":"Neural network-based non-linear A/D conversion","authors":"M. Bensenouci, H. Escid, M. Attari, A. Bensenouci","doi":"10.1109/CIRCUITSANDSYSTEMS.2015.7394082","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2015.7394082","url":null,"abstract":"This work describes how feed-forward Artificial Neural Networks (ANNs) can perform Analog-to-Digital (A/D) conversion with a linear and non-linear relationship between the analog input and the digital output in order to eliminate the linearization stage without modifying the analog-to-digital converter's elements and architecture. Adding to that, the speed of this A/D converter will not be reduced due to the unchanged conversion algorithm. Simulation for two types of non-linear input has been performed. The results are discussed and a future work is presented.","PeriodicalId":306918,"journal":{"name":"2015 IEEE International Circuits and Systems Symposium (ICSyS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124370578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Improvement on return-path-discontinuity issue through RLC termination for plating-via-stub 通过RLC终止对镀孔桩回程路径不连续问题的改进
2015 IEEE International Circuits and Systems Symposium (ICSyS) Pub Date : 2015-09-01 DOI: 10.1109/CIRCUITSANDSYSTEMS.2015.7394058
N. A. Khalid, N. Mahyuddin
{"title":"Improvement on return-path-discontinuity issue through RLC termination for plating-via-stub","authors":"N. A. Khalid, N. Mahyuddin","doi":"10.1109/CIRCUITSANDSYSTEMS.2015.7394058","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2015.7394058","url":null,"abstract":"Due to low cost and easy manufacturing, plated-through-hole (PTH) via has extensively deployed in multilayer board/package compared to other types of via. Via is extensively used to connect one layer to another layer. However, via transition might lead to return path discontinuity (RPD) issues due to stub if it is not properly handled. Stub is the unused length or portion of via due to the transition between respective signaling layers. Stub introduces impedance mismatched at the via transition due to unterminated excessive length and shunt capacitance, thus introduces signal integrity issue. In this paper, the RPD effect is studied based on the three different configuration of through hole via for microstrip to stripline via transition of 8-layer board. A 3D electromagnetic field simulator, HFSS will be used to model via stub with recommended stack-up. Subsequently, analysis of RC and proposed RLC termination were carried out on the plating-via-stub introduced at the bottom pad of via transition, targeting an improvement of signal integrity quality. The analysis focused on the S-parameter of return loss, insertion loss and eye diagram covering both time and frequency domain result in 14.8%, 20.8% and 15.6% improvement in eye opening for PTH, Drill and Split via configurations respectively.","PeriodicalId":306918,"journal":{"name":"2015 IEEE International Circuits and Systems Symposium (ICSyS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132656086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Reduced hardware architecture for energy-efficient IoT healthcare sensor nodes 简化了节能物联网医疗传感器节点的硬件架构
2015 IEEE International Circuits and Systems Symposium (ICSyS) Pub Date : 2015-09-01 DOI: 10.1109/CIRCUITSANDSYSTEMS.2015.7394071
Y. W. Lim, S. B. Daas, S. J. Hashim, R. Sidek, N. Kamsani, F. Rokhani
{"title":"Reduced hardware architecture for energy-efficient IoT healthcare sensor nodes","authors":"Y. W. Lim, S. B. Daas, S. J. Hashim, R. Sidek, N. Kamsani, F. Rokhani","doi":"10.1109/CIRCUITSANDSYSTEMS.2015.7394071","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2015.7394071","url":null,"abstract":"Healthcare solutions through the introduction of wearable healthcare devices are benefitting from Internet of Things technology. Though these small form-factor wearable devices promise great benefits, guaranteeing long device operating lifetime is yet the biggest challenge due to high-energy consumption. In this paper, a reduced hardware architecture system-on-chip targeting digital block design was proposed higher energy efficiency. The design has been verified by synthesizing into FPGA and implemented in silicon based on Silterra 180nm process. Results show that the proposed design achieved reduction up to 24% of leakage power and 15% of dynamic power reduction over reference design. In addition, 24.3% of excessive area was reduced by using the proposed reduced hardware architecture technique.","PeriodicalId":306918,"journal":{"name":"2015 IEEE International Circuits and Systems Symposium (ICSyS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134609486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
ASH1: A stack-based input/ output processor for USB operations ASH1:用于USB操作的基于堆栈的输入/输出处理器
2015 IEEE International Circuits and Systems Symposium (ICSyS) Pub Date : 2015-09-01 DOI: 10.1109/CIRCUITSANDSYSTEMS.2015.7394068
Abdullah Al-Dujaili, Lo Hai Hiung, S. Tan
{"title":"ASH1: A stack-based input/ output processor for USB operations","authors":"Abdullah Al-Dujaili, Lo Hai Hiung, S. Tan","doi":"10.1109/CIRCUITSANDSYSTEMS.2015.7394068","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2015.7394068","url":null,"abstract":"This paper describes a work in progress: ASH1, an 8-bit input/ output processor (IOP) that is designed to be able to perform USB operations. It has a stack-based architecture where most of the operations are done on the top elements of the stack. The instruction set consists of 17 14-bit instructions optimized for framing and driving software code. ASH1 communicates with the main processing unit (Master CPU) through a wishbone bus. It has been proven reliably at 50 MHz in an Altera Cyclone II FPGA device. With around 1400 FPGA slices and a maximum clock frequency of 90 MHz, ASH1 could make a good substitute for big USB IP Cores. Future work includes making ASH1 MAC Ethernet capable and USB2 compatible.","PeriodicalId":306918,"journal":{"name":"2015 IEEE International Circuits and Systems Symposium (ICSyS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116920020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of comparator with offset cancellation for 12-bit 1.6MS/s successive approximation ADC 用于12位1.6MS/s连续逼近ADC的偏移抵消比较器设计
2015 IEEE International Circuits and Systems Symposium (ICSyS) Pub Date : 2015-09-01 DOI: 10.1109/CIRCUITSANDSYSTEMS.2015.7394061
Hasmayadi Majid, Y. Yusoff
{"title":"Design of comparator with offset cancellation for 12-bit 1.6MS/s successive approximation ADC","authors":"Hasmayadi Majid, Y. Yusoff","doi":"10.1109/CIRCUITSANDSYSTEMS.2015.7394061","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2015.7394061","url":null,"abstract":"This paper presents the design and simulation of 3.3V comparator with offset cancellation implemented using 0.18μm XFAB's CMOS process technology. The comparator was designed for 12-bit 1.6MS/s Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). An offset cancellation technique was employed to improve comparator offset to 610μV. The comparator operates in 20MHz clock frequency while dissipates 858uW from a 3.3V supply. It occupies 56um × 118um silicon area.","PeriodicalId":306918,"journal":{"name":"2015 IEEE International Circuits and Systems Symposium (ICSyS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120950604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An efficient triple band microwave rectifier 一种高效的三波段微波整流器
2015 IEEE International Circuits and Systems Symposium (ICSyS) Pub Date : 2015-09-01 DOI: 10.1109/CIRCUITSANDSYSTEMS.2015.7394066
I. Adam, Mohd Fareq Abd Malek, M. Yasin, H. Rahim, N. Gomesh, A. T. Hussain
{"title":"An efficient triple band microwave rectifier","authors":"I. Adam, Mohd Fareq Abd Malek, M. Yasin, H. Rahim, N. Gomesh, A. T. Hussain","doi":"10.1109/CIRCUITSANDSYSTEMS.2015.7394066","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2015.7394066","url":null,"abstract":"This work presents the design and investigation of the 7-stage rectifier. A Modified dickson configuration is chosen, consists of two HSMS 2850 Schottky diodes and two through hole ceramic capacitors for each stage. The goal of this paper is to analyze the performance of the designed rectifier at its targeting frequency which are broadcasting, GSM and WiLAN frequency range. Rectifier properties such as number of stage and capacitance effects are analyzed and discussed in this paper. The result shows that the designed rectifier can operate well at the targeted frequencies.","PeriodicalId":306918,"journal":{"name":"2015 IEEE International Circuits and Systems Symposium (ICSyS)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117272328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Enhanced SPICE memristor model with dynamic ground 带动态接地的增强SPICE忆阻器模型
2015 IEEE International Circuits and Systems Symposium (ICSyS) Pub Date : 2015-09-01 DOI: 10.1109/CIRCUITSANDSYSTEMS.2015.7394079
Patrick W. C. Ho, F. Hatem, H. Almurib, T. N. Kumar
{"title":"Enhanced SPICE memristor model with dynamic ground","authors":"Patrick W. C. Ho, F. Hatem, H. Almurib, T. N. Kumar","doi":"10.1109/CIRCUITSANDSYSTEMS.2015.7394079","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2015.7394079","url":null,"abstract":"In this paper, an improved memristor SPICE model of [1] is presented by incorporating dynamic ground feature. Thus the proposed model enables the memristor to admit bidirectional current flow regardless of the manner it is connected to its voltage source and behaves similar to the electrical characteristics of the physical memristor. The simulation results of the proposed memristor model shows that they are in close agreement with experimental results.","PeriodicalId":306918,"journal":{"name":"2015 IEEE International Circuits and Systems Symposium (ICSyS)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124748592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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