Proceedings. VLSI and Computer Peripherals. COMPEURO 89最新文献

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The role of models in handling complexity, flexibility and reliability of human-computer interfaces 模型在处理人机界面的复杂性、灵活性和可靠性方面的作用
Proceedings. VLSI and Computer Peripherals. COMPEURO 89 Pub Date : 1989-05-08 DOI: 10.1109/CMPEUR.1989.93387
L. Bálint
{"title":"The role of models in handling complexity, flexibility and reliability of human-computer interfaces","authors":"L. Bálint","doi":"10.1109/CMPEUR.1989.93387","DOIUrl":"https://doi.org/10.1109/CMPEUR.1989.93387","url":null,"abstract":"General and specific aspects of modeling human-computer interfaces (HCIs) are investigated. Possibilities and methods of using structural architectures in interface construction together with the according hierarchy and modularity in HCI modeling are described. Efficiency and reliability in human-computer interaction are found to be dependent on the complexity and flexibility of the interfaces. The concept of universal, application-oriented, and application-specific HCI components is introduced. Methods of modeling HCIs and HCI modules are outlined, emphasizing the role of experiments made by fast computerized prototyping.<<ETX>>","PeriodicalId":304457,"journal":{"name":"Proceedings. VLSI and Computer Peripherals. COMPEURO 89","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132634095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Intelligent positron-electron-proton spectrometer detector interface VLSI electronics for a satellite instrument 用于卫星仪器的智能正电子质子光谱仪探测器接口VLSI电子器件
Proceedings. VLSI and Computer Peripherals. COMPEURO 89 Pub Date : 1989-05-08 DOI: 10.1109/CMPEUR.1989.93421
J. Suutari, H. Rantalainen, K. Ahola, H. Tenhunen
{"title":"Intelligent positron-electron-proton spectrometer detector interface VLSI electronics for a satellite instrument","authors":"J. Suutari, H. Rantalainen, K. Ahola, H. Tenhunen","doi":"10.1109/CMPEUR.1989.93421","DOIUrl":"https://doi.org/10.1109/CMPEUR.1989.93421","url":null,"abstract":"An intelligent peripheral mixed analog/digital advanced detector interface circuit (ADIC) has been designed to be used in a satellite instrument. The ADIC makes it possible to measure simultaneously the energies of positrons, electrons, and protons generated in the Sun during the high particle fluxes of solar flares. An effective processor interface design helps to remove signal-processing workload from the main CPU. An intelligent stand-alone interface is necessary because of the limited resources in harsh space environments. Sensitive charge integrators are used in interfaces to silicon strip detectors. Digital position information is produced without any A/D conversion schemes.<<ETX>>","PeriodicalId":304457,"journal":{"name":"Proceedings. VLSI and Computer Peripherals. COMPEURO 89","volume":"302 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133434292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fast, precise, and inexpensive AD-converters of a new time-division configuration for intelligent ohmic and capacitive sensors 用于智能欧姆和电容传感器的新型时分配置的快速,精确和廉价的ad转换器
Proceedings. VLSI and Computer Peripherals. COMPEURO 89 Pub Date : 1989-05-08 DOI: 10.1109/CMPEUR.1989.93417
K. Horn
{"title":"Fast, precise, and inexpensive AD-converters of a new time-division configuration for intelligent ohmic and capacitive sensors","authors":"K. Horn","doi":"10.1109/CMPEUR.1989.93417","DOIUrl":"https://doi.org/10.1109/CMPEUR.1989.93417","url":null,"abstract":"Discusses those types of intelligent sensors that have a passive sensing device with ohmic or capacitive pick-up elements. It is shown that by means of specific compensation methods and the time-division principle combined with a novel strategy of digital control, it is possible to reduce the effects of transfer drifts of the electronic components of the sensor circuitry, simplify the circuitry, achieve at lower resolutions (e.g., 8 b) the conversion speed of conventional dual-slope A/D converters, and allow higher resolutions (up to 20 b) at a reduced bandwidth.<<ETX>>","PeriodicalId":304457,"journal":{"name":"Proceedings. VLSI and Computer Peripherals. COMPEURO 89","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133442179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Logic synthesis for VLSI VLSI逻辑合成
Proceedings. VLSI and Computer Peripherals. COMPEURO 89 Pub Date : 1989-05-08 DOI: 10.1109/CMPEUR.1989.93472
B. Vergnieres, D. Bonifas
{"title":"Logic synthesis for VLSI","authors":"B. Vergnieres, D. Bonifas","doi":"10.1109/CMPEUR.1989.93472","DOIUrl":"https://doi.org/10.1109/CMPEUR.1989.93472","url":null,"abstract":"The authors present the current state of art of logic synthesis within IBM and some aspects developed at IBM Essonnes Component Development Laboratory. The application domain of logic synthesis is defined. Some high-level design languages are presented, since their practical features are essential in this process. The current synthesis approaches are detailed, with an emphasis on algebraic techniques. Examples are given of IBM machines designed with logic synthesis, and of an application to the optimization of an ASIC library.<<ETX>>","PeriodicalId":304457,"journal":{"name":"Proceedings. VLSI and Computer Peripherals. COMPEURO 89","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133751008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Head and media requirements for high density recording 磁头和介质要求高密度记录
Proceedings. VLSI and Computer Peripherals. COMPEURO 89 Pub Date : 1989-05-08 DOI: 10.1109/CMPEUR.1989.93354
W. Berghof
{"title":"Head and media requirements for high density recording","authors":"W. Berghof","doi":"10.1109/CMPEUR.1989.93354","DOIUrl":"https://doi.org/10.1109/CMPEUR.1989.93354","url":null,"abstract":"The extension of magnetic recording to very high areal density requires that all the critical parameters of the system be reduced to extremely small values. The recording head parameters have to be scaled down, as well as the media magnetic parameters and the media thickness. Furthermore, pulse-slimming equalization techniques are effective in increasing the recording density by reducing intersymbol interface and eliminating negative sidelobes. The author discusses the limitations of conventional ferrite heads, and the advantages of thin-film inductive heads deposited by sputtering and/or electrodeposition onto a very hard ceramic wafer the structure of the head elements being defined by photolithography and dry and wet etch steps, and thin-film magnetoresistive read heads. The latter are particularly advantageous on inner tracks of small-diameter disk drives where linear velocity is relatively slow. Integrating a magnetoresistive read head with an inductive write head not only improves the readback sensitivity but also solves track interference problems during reading, since the width of the read element can be made narrower than the width of the write head. Critical requirements for longitudinal-recording media in general and thin-film disks in particular are also considered.<<ETX>>","PeriodicalId":304457,"journal":{"name":"Proceedings. VLSI and Computer Peripherals. COMPEURO 89","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134222613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
VLSI based tools for monitoring bus communication channels 基于VLSI的总线通信通道监控工具
Proceedings. VLSI and Computer Peripherals. COMPEURO 89 Pub Date : 1989-05-08 DOI: 10.1109/CMPEUR.1989.93448
F. Gregoretti, F. Maddaleno
{"title":"VLSI based tools for monitoring bus communication channels","authors":"F. Gregoretti, F. Maddaleno","doi":"10.1109/CMPEUR.1989.93448","DOIUrl":"https://doi.org/10.1109/CMPEUR.1989.93448","url":null,"abstract":"An architecture for the run-time monitoring of the performance of a computer system is presented. In order to reduce the complexity of the system, a special integrated circuit has been designed, and the prototype integrated circuits are to be used in a first experimental realization of the system. The first prototype has been implemented in 3- mu m CMOS technology, contains 16 associative words, has a complexity of 11000 transistors, and has read/write and match times of 110 ns and 90 ns, respectively, due to a rather poor design of I/O pads. A second version in a 2- mu m technology is currently under fabrication and is expected to reduce these times by one half.<<ETX>>","PeriodicalId":304457,"journal":{"name":"Proceedings. VLSI and Computer Peripherals. COMPEURO 89","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134191885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The future of optical recording 光学记录的未来
Proceedings. VLSI and Computer Peripherals. COMPEURO 89 Pub Date : 1989-05-08 DOI: 10.1109/CMPEUR.1989.93322
G. E. Thomas
{"title":"The future of optical recording","authors":"G. E. Thomas","doi":"10.1109/CMPEUR.1989.93322","DOIUrl":"https://doi.org/10.1109/CMPEUR.1989.93322","url":null,"abstract":"Summary form only given. The optical recording technologies currently available are reviewed, and a brief summary of the principles which govern their performance is given. Possible improvements in three key performance areas are addressed. These areas are the data storage density (currently near 100 Mb/cm/sup 2/), the data rate, and the access time. Such improvements require new developments in all of the subsystems of optical recording: lasers, optics, servo systems, electronics, and media. A review of these new developments is given, and the feasibility of combining the individual innovations to produce highly advanced systems is discussed.<<ETX>>","PeriodicalId":304457,"journal":{"name":"Proceedings. VLSI and Computer Peripherals. COMPEURO 89","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131755370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Smart humidity sensors-challenges and benefits of computer measurement systems 智能湿度传感器——计算机测量系统的挑战和优势
Proceedings. VLSI and Computer Peripherals. COMPEURO 89 Pub Date : 1989-05-08 DOI: 10.1109/CMPEUR.1989.93407
R. Jachowicz
{"title":"Smart humidity sensors-challenges and benefits of computer measurement systems","authors":"R. Jachowicz","doi":"10.1109/CMPEUR.1989.93407","DOIUrl":"https://doi.org/10.1109/CMPEUR.1989.93407","url":null,"abstract":"Many different measurement methods, depending on the humidity range and required accuracy, are used for humidity sensors. The author reviews the properties of some of these sensors, considering the potential advantages of computer control and the requirements such control imposes on the sensor element itself.<<ETX>>","PeriodicalId":304457,"journal":{"name":"Proceedings. VLSI and Computer Peripherals. COMPEURO 89","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116006736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Packaging of VLSI devices VLSI器件封装
Proceedings. VLSI and Computer Peripherals. COMPEURO 89 Pub Date : 1989-05-08 DOI: 10.1109/CMPEUR.1989.93485
H. Reichl
{"title":"Packaging of VLSI devices","authors":"H. Reichl","doi":"10.1109/CMPEUR.1989.93485","DOIUrl":"https://doi.org/10.1109/CMPEUR.1989.93485","url":null,"abstract":"VLSI technologies are characterized by a drastic reduction of component size and the economical production of large-area chips. Electrical and geometrical characteristics of modern VLSI chips require a synchronized progress in the development of chip and board technologies. Furthermore, alternative hierarchies within electronic systems, such as the application of multichip modules or microsystems, must be considered. The geometrical and electrical chip parameters are discussed, and the requirements for future packaging technologies are summarized.<<ETX>>","PeriodicalId":304457,"journal":{"name":"Proceedings. VLSI and Computer Peripherals. COMPEURO 89","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116529063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A VLSI-based intelligent peripheral for a marine simulator computer system 基于vlsi的船舶模拟计算机系统智能外设
Proceedings. VLSI and Computer Peripherals. COMPEURO 89 Pub Date : 1989-05-08 DOI: 10.1109/CMPEUR.1989.93384
L.S. Dooley
{"title":"A VLSI-based intelligent peripheral for a marine simulator computer system","authors":"L.S. Dooley","doi":"10.1109/CMPEUR.1989.93384","DOIUrl":"https://doi.org/10.1109/CMPEUR.1989.93384","url":null,"abstract":"The author presents a new design strategy for the artificial reproduction of ship-board-generated sounds for temporal marine simulators. An overview is furnished of previous analog and digital synthesis techniques. A coherent design rationale for a VLSI-based digital sound synthesizer prototype is discussed, together with a full description of the interface bus, which permits very fast communications with the main simulator computer. A flow chart of the sound synthesizer board and a circuit diagram of its VLSI realization are provided.<<ETX>>","PeriodicalId":304457,"journal":{"name":"Proceedings. VLSI and Computer Peripherals. COMPEURO 89","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115880707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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