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2009 IEEE International SOC Conference (SOCC)最新文献

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A novel high-efficiency partial-parallel context modeling architecture for EBCOT in JPEG2000 基于JPEG2000的EBCOT高效部分并行上下文建模
2009 IEEE International SOC Conference (SOCC) Pub Date : 2009-09-11 DOI: 10.1109/SOCCON.2009.5398095
Xin Zhao, A. Erdogan, T. Arslan
{"title":"A novel high-efficiency partial-parallel context modeling architecture for EBCOT in JPEG2000","authors":"Xin Zhao, A. Erdogan, T. Arslan","doi":"10.1109/SOCCON.2009.5398095","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398095","url":null,"abstract":"In this paper, we present a novel Context Modeling (CM) architecture used in JPEG2000 encoder targeting next generation of cameras. The implementation is based on a newly emerging coarsegrained Dynamically Reconfigurable (DR) processor. A novel partial parallel architecture for the CM is introduced which can be easily tailored for the target DR processor in order to achieve higher performance results. Simulation results show that the resulting architecture provides throughput reaching up to 60.82MS/s, representing 1.2x speed up compared to previous parallel CM architectures.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121143161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A multi-level simulation approach in a Simulink-based design tool for FPGAs 基于simulink的fpga设计工具中的多级仿真方法
2009 IEEE International SOC Conference (SOCC) Pub Date : 2009-09-01 DOI: 10.1109/SOCCON.2009.5398105
M. Tranchero, L. Reyneri
{"title":"A multi-level simulation approach in a Simulink-based design tool for FPGAs","authors":"M. Tranchero, L. Reyneri","doi":"10.1109/SOCCON.2009.5398105","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398105","url":null,"abstract":"This paper describes how simulation across multi-abstraction level problem has been solved in CodeSimulink environment, a high-level design tool for FPGAs and DSPs. We detail how we achieve the desired behavior at almost every considered level (i.e., Simulink, RTL and on-chip). We also show some results on simple applications to validate the approach.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122640446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low power RS codec using cell-based reconfigurable processor 采用基于单元的可重构处理器的低功耗RS编解码器
2009 IEEE International SOC Conference (SOCC) Pub Date : 2009-09-01 DOI: 10.1109/SOCCON.2009.5398042
A. El-Rayis, Xin Zhao, T. Arslan, A. Erdogan
{"title":"Low power RS codec using cell-based reconfigurable processor","authors":"A. El-Rayis, Xin Zhao, T. Arslan, A. Erdogan","doi":"10.1109/SOCCON.2009.5398042","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398042","url":null,"abstract":"This paper describes a low power reconfigurable processor for Reed Solomon (RS) Codec. The Reed Solomon Processor targets handheld devices that use emerging communication standards such as WiMAX and DVB-H. Different design approaches and optimization techniques have been applied in order to enhance the processor throughput and reduce its energy consumption. The throughput achieved is up to 200 Mbps and 92 Mbps for the encoder and decoder respectively. Associated dynamic energy consumption is in the range of 0.34 to 1.17μϋ demonstrating a design suitable for present and future handheld devices.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"2021 41","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114048085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Improving Operational transconductance Amplifier (OTA) gain-bandwidth tradeoff using gate-underlap MOSFETs 利用栅极覆盖mosfet改善运算跨导放大器(OTA)增益与带宽的权衡
2009 IEEE International SOC Conference (SOCC) Pub Date : 2009-09-01 DOI: 10.1109/SOCCON.2009.5398084
A. Kranti, G. A. Armstrong
{"title":"Improving Operational transconductance Amplifier (OTA) gain-bandwidth tradeoff using gate-underlap MOSFETs","authors":"A. Kranti, G. A. Armstrong","doi":"10.1109/SOCCON.2009.5398084","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398084","url":null,"abstract":"The present work highlights the usefulness of underlap channel design in improving gain-bandwidth trade-off in analog circuit design. It is demonstrated that high values of intrinsic voltage gain (AVO_OTA) > 55 dB and unity gain frequency (fT_OTA) ~ 57 GHz of a folded cascode Operational transconductance Amplifier (OTA) can be achieved with gate-underlap channel design in 60 nm MOSFETs. These values correspond to a 15 dB improvement in AVO_OTA and a 3 fold enhancement in fT_OTA over a conventional non-underlap design. Gate-underlap OTA preserves functionality at high temperatures (550 K) by exhibiting high values of AVO_OTA (42 dB) and fT_OTA (24 GHz). Results present new opportunities for low voltage analog circuit design with future technologies.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129442873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Adaptive admission control on the SpiNNaker MPSoC SpiNNaker MPSoC的自适应接纳控制
2009 IEEE International SOC Conference (SOCC) Pub Date : 2009-09-01 DOI: 10.1109/SOCCON.2009.5398050
Shufan Yang, S. Furber, L. Plana
{"title":"Adaptive admission control on the SpiNNaker MPSoC","authors":"Shufan Yang, S. Furber, L. Plana","doi":"10.1109/SOCCON.2009.5398050","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398050","url":null,"abstract":"End-to-end communication service is critical to maximise both flexibility and performance on a Multi-Processor System-on-Chip (MPSoC). We introduce adaptive admission control to ensure fair bandwidth allocation to each processing node on an MPSoC platform. The results from the Matlab system model show good agreement with the experimental results from the HDL model. Consequently, the Matlab model can be used as an effective prototyping toolkit.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129041309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Performance comparison of two low power wide tuning range VCOs in 90 nm CMOS 两种90nm CMOS低功耗宽调谐范围压控振荡器的性能比较
2009 IEEE International SOC Conference (SOCC) Pub Date : 2009-09-01 DOI: 10.1109/SOCCON.2009.5398101
S. Ren, R. Siferd
{"title":"Performance comparison of two low power wide tuning range VCOs in 90 nm CMOS","authors":"S. Ren, R. Siferd","doi":"10.1109/SOCCON.2009.5398101","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398101","url":null,"abstract":"Two 90 nm CMOS low power wide tuning range VCO designs are presented. A Dual Delay Ring VCO has a tuning range of 63%, consumes 6.5 mW at 6 GHz, and has a phase noise of −92d Bc/Hz at 1 MHz offset at 6 GHz center frequency. A Relaxation VCO has a tuning range of 183%, consumes 0.9 mW at 6 GHz, and has a phase noise of −83 dBc/Hz at 1 MHz offset at 6 GHz center frequency. The supply voltage is 1.2 v.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116470331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
High-performance architecture of H.264 integer-pixel motion estimation IP for real-time 1080HD video CODEC 用于实时1080HD视频编解码器的H.264整像素运动估计IP的高性能架构
2009 IEEE International SOC Conference (SOCC) Pub Date : 2009-09-01 DOI: 10.1109/SOCCON.2009.5398003
Hoyoung Chang, Soojin Kim, Seonyoung Lee, Kyeongsoon Cho
{"title":"High-performance architecture of H.264 integer-pixel motion estimation IP for real-time 1080HD video CODEC","authors":"Hoyoung Chang, Soojin Kim, Seonyoung Lee, Kyeongsoon Cho","doi":"10.1109/SOCCON.2009.5398003","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398003","url":null,"abstract":"We propose a new H.264 integer-pixel motion estimation algorithm and circuit architecture to improve the processing speed. The proposed circuit supports 7 kinds of variable block sizes and generates 41 motion vectors. The implemented IP based on the proposed algorithm and architecture processes 60 image frames per second for 1080HD video at the operating frequency of 45.5MHz.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121665706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
High path-count multirate Rayleigh fading channel simulator with time-multiplexed datapath 具有时间复用数据路径的高路径数多速率瑞利衰落信道模拟器
2009 IEEE International SOC Conference (SOCC) Pub Date : 2009-09-01 DOI: 10.1109/SOCCON.2009.5398008
S. F. Fard, A. Alimohammad, B. Cockburn, C. Schlegel
{"title":"High path-count multirate Rayleigh fading channel simulator with time-multiplexed datapath","authors":"S. F. Fard, A. Alimohammad, B. Cockburn, C. Schlegel","doi":"10.1109/SOCCON.2009.5398008","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398008","url":null,"abstract":"In this paper we introduce an especially compact architecture for the high-throughput simulation of Rayleigh fading channels and hence the verification of high path count wireless systems at hardware speeds. The new architecture utilizes a time-multiplexed scheme that allows the fading channel simulator to be fit into a small fraction of a field-programmable gate array (FPGA). Implementing a 64-path fading channel simulator on a Xilinx Virtex-II Pro XC2VP100-6 FPGA uses only 29% of the configurable slices, 2% of the block memories, and 1% of the dedicated multipliers, while generating 64×238 million complex-valued fading samples per second.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114835278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
FPGA-based SoC for transcoding H264/AVC-SVC with low latency and high bitrate entropy coding 基于fpga的H264/AVC-SVC转码SoC，具有低延迟和高比特熵编码
2009 IEEE International SOC Conference (SOCC) Pub Date : 2009-09-01 DOI: 10.1109/SOCCON.2009.5398004
M. Guarisco, H. Rabah, Y. Berviller, S. Weber, Said Belkouch
{"title":"FPGA-based SoC for transcoding H264/AVC-SVC with low latency and high bitrate entropy coding","authors":"M. Guarisco, H. Rabah, Y. Berviller, S. Weber, Said Belkouch","doi":"10.1109/SOCCON.2009.5398004","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398004","url":null,"abstract":"Scalable Video Coding extension of H.264 standard is very suitable for content adaptation and addressing different terminals. However, in various cases it is necessary to perform transcoding in video coding layer requiring tremendous computation and hardware acceleration. In this paper, we present an efficient hardware architecture of a CAVLC codec based on a new method that provides a constant and reduced latency. The presented method calculates the 16 DCT coefficients in parallel. The results of hardware implementation targeting a Xilinx Virtex 5 FPGA are presented.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127709566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An instruction set architecture independent design method for embedded OFDM-based software defined transmitter 基于ofdm的嵌入式软件定义发射机指令集体系结构独立设计方法
2009 IEEE International SOC Conference (SOCC) Pub Date : 2009-09-01 DOI: 10.1109/SOCCON.2009.5398058
Jui-Chieh Lin, Min-Han Hsieh, Ming-Jung Fan-Chiang, Chu Yu, Sao-Jie Chen, Y. Hu
{"title":"An instruction set architecture independent design method for embedded OFDM-based software defined transmitter","authors":"Jui-Chieh Lin, Min-Han Hsieh, Ming-Jung Fan-Chiang, Chu Yu, Sao-Jie Chen, Y. Hu","doi":"10.1109/SOCCON.2009.5398058","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398058","url":null,"abstract":"An instruction set architecture independent design method targeted on embedded software defined radio is proposed. Without the aid of specified instructions, this work focuses on cycle-efficient implementation of bit-oriented operations on word-based processors. High portability between platforms is achieved and demonstrated with an IEEE 802.11a (WiFi) transmitter implemented in C language on both Sandbridge Technologies© Inc. SB3011 baseband processor evaluation board and Texas Instruments© Inc. TMS320 C64x digital signal processor. More than 99% instruction cycle reductions are observed on both platforms.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121452493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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