High path-count multirate Rayleigh fading channel simulator with time-multiplexed datapath

In this paper we introduce an especially compact architecture for the high-throughput simulation of Rayleigh fading channels and hence the verification of high path count wireless systems at hardware speeds. The new architecture utilizes a time-multiplexed scheme that allows the fading channel simulator to be fit into a small fraction of a field-programmable gate array (FPGA). Implementing a 64-path fading channel simulator on a Xilinx Virtex-II Pro XC2VP100-6 FPGA uses only 29% of the configurable slices, 2% of the block memories, and 1% of the dedicated multipliers, while generating 64×238 million complex-valued fading samples per second.