{"title":"Burst and unidirectional error detecting codes","authors":"S. Al-Bassam, B. Bose, R. Venkatesan","doi":"10.1109/FTCS.1991.146689","DOIUrl":"https://doi.org/10.1109/FTCS.1991.146689","url":null,"abstract":"It is proved that codes devised by J. Berger (see Inf., and Control. vol.4, p.68-73, (1961)) that detect random bursts of length b and simultaneously detect any number of unidirectional errors (b-bED/AUED codes) are optimal. The construction is modified in two ways: (1) to obtain b-bED/s-UED codes in which a random burst of length b and up to s unidirectional errors are detected, and (2) to obtain b-bED/s-UbED codes in which a random burst of length b and a unidirectional burst of length s are detected. A lower bound on the number of check bits for such codes is obtained. The lower bounds indicate that the proposed b-bED/s-UED codes are close to optimal and the b-bED/s-UbED codes are asymptotically optimal.<<ETX>>","PeriodicalId":300397,"journal":{"name":"[1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116004204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Performability analysis of distributed real-time systems with repetitive task invocation","authors":"S. Islam, H. Ammar","doi":"10.1109/FTCS.1991.146685","DOIUrl":"https://doi.org/10.1109/FTCS.1991.146685","url":null,"abstract":"An algorithm and a methodology for the performability analysis of a class of repairable distributed real-time systems are presented. Distributed real-time workloads generally consist of repetitive concurrent tasks with known cycle and deadline times. The planning cycle of real-time distributed systems, which normally consists of several task invocations, is first identified. A repairable distributed real-time system that can be described by a cyclic Markov reward model between invocation tasks is considered. The performability distribution at the end of the planning cycle is determined by performing repeated convolution of performability densities between task invocations. This convolution operation is efficiently done using the Laguerre coefficients. The algorithm numerically determines both moment and distribution of performability in O(N/sup 3/).<<ETX>>","PeriodicalId":300397,"journal":{"name":"[1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116380746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Approaches to design of temporary blackout handling capabilities and an evaluation with a real-time tightly coupled network testbed","authors":"K. Kim, W. Guan, A. Damm, J. Rohr","doi":"10.1109/FTCS.1991.146703","DOIUrl":"https://doi.org/10.1109/FTCS.1991.146703","url":null,"abstract":"The problem of designing real-time tightly coupled networks (TCNs) that can survive through temporary blackout (TB) events that disrupt orderly operation of electronic components and erase the contents of all registers and RAMs is treated. Three approaches are considered. The first, in existence for some time although not practiced extensively, relies on the software designer for highly application-dependent design of all parts of TB handling procedures. The second is a fully application-transparent approach to state saving based on the use of recoverable regions. The third, a compromise between the first two approaches, uses time-driven insertion of saving points and relies on the software designer to determine the membership of the state vector. An experiment that involved designing TB handling capabilities into a real-time TCN testbed using each approach is reported. The testbed-based evaluation results validated the practicality of the two new approaches and indicated the complementary relationship between them and the first approach.<<ETX>>","PeriodicalId":300397,"journal":{"name":"[1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium","volume":"256 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122657113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"State space generation for degradable multiprocessor systems","authors":"B. Aupperle, J. F. Meyer","doi":"10.1109/FTCS.1991.146678","DOIUrl":"https://doi.org/10.1109/FTCS.1991.146678","url":null,"abstract":"Degradable multiprocessors can have a large number of different structural configurations (states) after being altered by faults. Many such states may be equivalent relative to their overall effect on a system's ability to perform. Hence, depending on the performability measure, the number of states can often be reduced to a much smaller set of representative configurations, one for each equivalence class. An algorithm that generates these representatives and determines the size of each equivalence class is presented. The algorithm assumes that performance is invariant under structural symmetries and thus employs a symmetry permutation group. The information so obtained permits construction of a stochastic process model that supports the performability measure in question. The group-theoretic concepts on which the algorithm is based are presented, and its complexity is considered. The use of the algorithm to construct a performability model is illustrated, and possible extensions are addressed.<<ETX>>","PeriodicalId":300397,"journal":{"name":"[1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128692522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Construction and analysis of fault-secure multiprocessor schedules","authors":"Dechang Gu, D. Rosenkrantz, S. Ravi","doi":"10.1109/FTCS.1991.146650","DOIUrl":"https://doi.org/10.1109/FTCS.1991.146650","url":null,"abstract":"Issues involved in the design and analysis of fault-secure schedules for multiprocessor systems are investigated. A formal characterization of fault-security for a single fault is developed and generalized for multiple faults. The single fault characterization is used in the construction of fault-secure schedules for several classes of computation trees. The schemes produce schedules that are either shorter than or use fewer processors than the schedules produced by currently known methods. Further, lower bounds on schedule lengths are developed to prove that the schedules produced by the schemes are optimal or close to optimal. The characterization for multiple faults leads to an efficient algorithm to determine whether a given schedule is fault-secure for any fixed number of faults. It is shown that when the number of faults is not fixed, the problem of determining whether a schedule is fault-secure is computationally intractable.<<ETX>>","PeriodicalId":300397,"journal":{"name":"[1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131118000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"TSUNAMI: a path oriented scheme for algebraic test generation","authors":"T. Stanion, D. Bhattacharya","doi":"10.1109/FTCS.1991.146630","DOIUrl":"https://doi.org/10.1109/FTCS.1991.146630","url":null,"abstract":"An algorithm is presented for generating tests for single stuck line faults using a combination of algebraic processing and conventional path oriented search. Unlike conventional test generation algorithms, this algorithm uses algebraic methods to determine the complete set of input assignments that will propagate an error signal through a gate in a path to a primary output. The algorithm uses ordered binary decision diagrams (BDDs) for algebraic processing. For a large number of circuits that are amenable to analysis using BDDs, the algorithm is faster than previous algebraic methods. The algorithm has been implemented as the program TSUNAMI. Experimental results demonstrate that for most circuits TSUNAMI can generate test sets for all faults in fairly small amounts of time and is very efficient for hard-to-detect and redundant faults. Moreover, since a large set of tests is generated for each fault, these sets can be compacted to a very high degree. Using benchmark circuits as a reference, TSUNAMI obtains test sets up to 70% smaller than test sets generated by conventional algorithms.<<ETX>>","PeriodicalId":300397,"journal":{"name":"[1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127986837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A fault-tolerant FFT processor","authors":"M. Tsunoyama, S. Naito","doi":"10.1109/FTCS.1991.146651","DOIUrl":"https://doi.org/10.1109/FTCS.1991.146651","url":null,"abstract":"A scheme for concurrent fault detection by recomputing and a fault-tolerant FFT processor using the scheme are proposed. An FFT processor with perfect shuffle is considered. The realization of the processor is based on a linear cellular automaton (LCA) model having the constant-weight and equidistance properties. When a fault occurs in the processor, the fault is detected concurrently and the processor is reconfigured by replacing the faulty butterfly unit with a normal one according to the state of the processor. The reconfiguration can be made within a clock period by making a state transition based on the LCA model and by reconnecting the butterfly units according to the new state. The processor can be reconfigured quickly, so that it can be used for highly reliable real-time data processing systems.<<ETX>>","PeriodicalId":300397,"journal":{"name":"[1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130921389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Exploiting instruction-level resource parallelism for transparent, integrated control-flow monitoring","authors":"M. Schuette, John Paul Shen","doi":"10.1109/FTCS.1991.146680","DOIUrl":"https://doi.org/10.1109/FTCS.1991.146680","url":null,"abstract":"Available resource-driven control-flow monitoring (ARC), a method for detecting transient errors by using idle resources in processor architectures that use increased degrees of instruction-level parallelism to achieve performance goals, is presented. The focus is on concurrent detection of control-flow errors (CFEs) in VLIW processors. Previous work is reviewed, and ARC monitoring is described as a monitoring computation (MC) that executes concurrently with and continuously monitors the execution of the application computation (AC). The algorithm that integrates the MC into the AC is presented. An analytical derivation of ARC's error coverage is given, and results of applying ARC to four benchmark programs on an actual VLIW processor are reported. Results show that for all the benchmarks, all of the additional operations required by ARC can make use of idle resources, achieving a detection coverage of >99% in all cases. The performance overhead of ARC is found to be negligible, even for programs with relatively few idle resources available.<<ETX>>","PeriodicalId":300397,"journal":{"name":"[1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium","volume":"92 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126131534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An architectural level test generator for a hierarchical design environment","authors":"Jaushin Lee, J. Patel","doi":"10.1109/FTCS.1991.146631","DOIUrl":"https://doi.org/10.1109/FTCS.1991.146631","url":null,"abstract":"Most state-of-the-art automatic test pattern generators (ATPGs) require a detailed gate level representation for the circuits under test, information that either does not exist or may not be available to the test engineers in a hierarchical design environment. An ATPG methodology working at an architectural level is proposed to exploit the hierarchy of the design and relieve the dependence on the gate level information. The test set for each high level primitive is pregenerated by any low-level sequential ATPG tool, based on any possible fault model. The test patterns in these test sets are justified and the fault effects are propagated at high level. Due to the fault collapsing effect, several data types have been defined for the manipulation of all possible fault effects. When conflict occurs and the backtracking mechanism is invoked, a novel tracing technique and an indexed backtracking technique are used to make high-level decisions.<<ETX>>","PeriodicalId":300397,"journal":{"name":"[1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125402980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A multiple-fault tolerant sorting network","authors":"Jianli Sun, J. Gecsei","doi":"10.1109/FTCS.1991.146673","DOIUrl":"https://doi.org/10.1109/FTCS.1991.146673","url":null,"abstract":"Fault tolerance of balanced sorting networks (BSNs), which have the same performance bound as the Batcher efficient sorting networks, is discussed. Preliminary studies of fault tolerance in a BSN which demonstrated 1-fault tolerance with and without redundant comparators and external permuters and 2-fault tolerance requiring redundancy are reviewed. The present study further develops a k-fault-tolerant BSN design, where k>or=2 can be arbitrary in principle, even without redundancy. The performance analysis shows that the new designs achieve much higher probabilities of correct sorting in the presence of faulty comparators than the previously reported designs.<<ETX>>","PeriodicalId":300397,"journal":{"name":"[1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132744745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}