Exploiting instruction-level resource parallelism for transparent, integrated control-flow monitoring

Available resource-driven control-flow monitoring (ARC), a method for detecting transient errors by using idle resources in processor architectures that use increased degrees of instruction-level parallelism to achieve performance goals, is presented. The focus is on concurrent detection of control-flow errors (CFEs) in VLIW processors. Previous work is reviewed, and ARC monitoring is described as a monitoring computation (MC) that executes concurrently with and continuously monitors the execution of the application computation (AC). The algorithm that integrates the MC into the AC is presented. An analytical derivation of ARC's error coverage is given, and results of applying ARC to four benchmark programs on an actual VLIW processor are reported. Results show that for all the benchmarks, all of the additional operations required by ARC can make use of idle resources, achieving a detection coverage of >99% in all cases. The performance overhead of ARC is found to be negligible, even for programs with relatively few idle resources available.<>