{"title":"Alternative architectures for video signal processing","authors":"W. Wolf","doi":"10.1109/IWV.2000.844521","DOIUrl":"https://doi.org/10.1109/IWV.2000.844521","url":null,"abstract":"This paper looks at trends in architectures for video processing. As levels of integration has increased, video architectures have moved from dedicated to programmable. Programmable architectures continue to evolve as we move into the systems-on-silicon era. The promise of integrated memory systems is a particularly appealing prospect for improved video processing architectures.","PeriodicalId":300014,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134214133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Specification and validation of information processing systems by process encapsulation and symbolic execution","authors":"W. Boßung, T. Geyer, S. Huss, L. Wehmeyer","doi":"10.1109/IWV.2000.844535","DOIUrl":"https://doi.org/10.1109/IWV.2000.844535","url":null,"abstract":"A process notation based on a functional partitioning of a new system is proposed as a high-level codesign model for specification, evaluation, and implementation purposes. A well-defined computational model allows the synchronization and activation of concurrent processes. The design environment includes the refinement steps from scheduling with dynamic processes via simplified scheduling/execution methods to the complete implementation. The relationship between specified behavioral classes and implemented states in the final core programs is the key issue in this development flow. Time uncritical parts are implemented in a heterogeneous environment communicating via a standard communication protocol. On the other hand, time critical processes and process connections can be implemented in C/sup ++/ using SystemC, thus forming core programs encapsulated in a shell to fit the introduced and implemented activation rules. An example from the world of digital image processing systems illustrates the approach.","PeriodicalId":300014,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121300448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Mead-Conway VLSI design approach and system design challenges ahead","authors":"L. Conway","doi":"10.1109/IWV.2000.844520","DOIUrl":"https://doi.org/10.1109/IWV.2000.844520","url":null,"abstract":"What should the students of today be learning and doing to prepare them for system design 10 years from now? What will be the biggest challenges facing them at that time? Then too, where are the biggest opportunities for research impact right now? To help us think about such questions, we'll look back 25 years and reflect on some lessons from the early VLSI adventures of the late 70's. We'll see how separate disciplines were merged to create a new, simplified design methodology. We'll see how QTA implementation provided students and researchers with means to rapidly explore new design spaces opened by these methods. And we'll look at how a unique university/industry/government collaboration supported and motivated all these explorations. Looking ahead, we'll speculate about whether we might be at a similar \"break-point\" in complexity and system design challenges, and about the possibility that new innovations in system design could re-revolutionize microelectronics.","PeriodicalId":300014,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era","volume":"291 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115536301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Emerging trends in VLSI test and diagnosis","authors":"Y. Zorian","doi":"10.1109/IWV.2000.844524","DOIUrl":"https://doi.org/10.1109/IWV.2000.844524","url":null,"abstract":"As the move to very deep submicron VLSI devices pushes the threshold of semiconductor technology, conventional test and diagnosis methods become inadequate and costly. The new level of complexity driven by core-based system-chips demands that designers alter the way they approach chip development in order to keep up with diminishing time-to-market requirements and stay within budgets. Embedded test enables the production of higher-quality devices in less time. The use of embedded test raises margins and significantly reduces the time required for system verification, test and debug. This paper addresses discusses embedded test technology and analyzes its impact on time-to-market, product quality and cost.","PeriodicalId":300014,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125527103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low power VLSI architecture for 2D-mesh video object motion tracking","authors":"Wael Badawy, M. Bayoumi","doi":"10.1109/IWV.2000.844532","DOIUrl":"https://doi.org/10.1109/IWV.2000.844532","url":null,"abstract":"This paper presents a low power VLSI architecture for video object motion tracking. Power has been reduced at both algorithmic and arithmetic levels. The video object is modeled as a 2D hierarchical structured mesh, where the deformation of the mesh represents the dynamics of the object across the video sequence. The algorithm benefits from the small number of bits that describe the mesh topology. Low power has been achieved in the algorithm level by: (1) modeling the mesh into independent triangular patches that can be processed in parallel, (2) each patch is hierarchical triangulated using structured technique, which can be pipelined using simple unit, and (3) using the three steps motion estimation algorithm to simplify the motion estimation of the mesh nodes. On the arithmetic level, low power has been achieved by using multiplication-free affine transformation because of the followed triangle topology. A VLSI architecture is developed based on the proposed algorithm. The architecture consists of two main parts, a mesh-based motion estimation unit and a mesh-based motion compensation unit. The first unit is based on parallel block matching motion estimation to optimize the latency. The second uses parallel threads. Each thread implements a pipelined chain of scalable multiplication-free affine units. The architecture has been prototyped and its performance measures have been evaluated. This processor can be used in online object-based video applications such as in MPEG-4, and VRML.","PeriodicalId":300014,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132691009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"PicoRadio: Ad-hoc wireless networking of ubiquitous low-energy sensor/monitor nodes","authors":"J. Rabaey, J. Ammer, J. L. D. Silva, D. Patel","doi":"10.1109/IWV.2000.844522","DOIUrl":"https://doi.org/10.1109/IWV.2000.844522","url":null,"abstract":"One of the most compelling challenges of the next decade is the solution of the \"last meter\" problem, which extends the network into the end-user data-collection and monitoring devices. This paper discusses the challenges and opportunities of a \"PicoRadio Network\" that supports the assembly of an an-hoc wireless network of meso-scale, low-cost and low-energy sensor and monitor nodes.","PeriodicalId":300014,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130981531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"RT-level interconnect optimization in DSM regime","authors":"S. Katkoori, S. Alupoaei","doi":"10.1109/IWV.2000.844543","DOIUrl":"https://doi.org/10.1109/IWV.2000.844543","url":null,"abstract":"We propose global-net clustering based RT-level datapath design methodology. Static timing analysis identifies critical nets and critical primary input/output paths. Net clustering (based shared macro-cells and criticality) yields clusters wherein each cluster has strongly interdependent nets. Clusters and nets within every cluster are prioritized based on number of critical nets, number of nets, and the total macro-cell area. We propose two approaches to generate layouts at RTL: constructive (cluster growth) approach and iterative improvement based (simulated annealing) approach. For datapaths implemented in 0.35 /spl mu/m technology, for both approaches, we achieved an average decrease of 54% in longest wirelength and 53% in overall wirelength.","PeriodicalId":300014,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114840473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A low-latency FIFO for mixed-clock systems","authors":"Tiberiu Chelcea, S. Nowick","doi":"10.1109/IWV.2000.844540","DOIUrl":"https://doi.org/10.1109/IWV.2000.844540","url":null,"abstract":"This paper presents a low-latency FIFO design that interfaces subsystems on a chip working at different speeds. First, a single-clock domain design is introduced, which is then used as a basis for a mixed-clock version. Finally, the design is adapted to work between subsystems with very long interconnection delays. The designs can be made arbitrarily robust with regard to metastability and clock frequencies.","PeriodicalId":300014,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115457669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An empirical and analytical comparison of delay elements and a new delay element design","authors":"N.R. Mahapatra, S. V. Garimella, A. Tareen","doi":"10.1109/IWV.2000.844534","DOIUrl":"https://doi.org/10.1109/IWV.2000.844534","url":null,"abstract":"This paper comprehensively reviews five different delay element architectures for use in CMOS VLSI design. The first four delay elements that we analyze are already in general use; they are the transmission gate, cascaded inverters, thyristor, and voltage-controlled delay element. The fifth delay element, a transmission gate with Schmitt trigger, is a new architecture that we are proposing in this paper. We compare these delay elements, both analytically and through simulations, in terms of four important parameters: delay, signal integrity, power consumption, and area, and find that they have widely varying characteristics. Depending upon the delay value required in an application, results presented in this paper will enable a designer to select the most appropriate delay element that meets signal integrity, power consumption, and area specifications.","PeriodicalId":300014,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133608629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Nicolescu, P. Coste, F. Hessel, P. LeMarrec, A. Jerraya
{"title":"Multilanguage design of a robot arm controller: Case study","authors":"G. Nicolescu, P. Coste, F. Hessel, P. LeMarrec, A. Jerraya","doi":"10.1109/IWV.2000.844526","DOIUrl":"https://doi.org/10.1109/IWV.2000.844526","url":null,"abstract":"This paper discusses a case study, the multilanguage design of a robot arm controller. The system is composed of two parts: the controller and the motors of the robot arm. The design starts with a multilanguage system-level specification. SDL was used for the description of the controller and Matlab was used for the description of the physical behavior of the motors. The multilanguage design flow includes the refinement of the modules and the refinement of the communication between these modules described in different languages. In order to validate the overall system through the design steps, cosimulation is performed at different levels of abstraction. This experiment shows that system level model may provide an early mock-up of the design before refining the intermodule communication.","PeriodicalId":300014,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129506773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}