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Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era最新文献

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Reconfigurable low energy multiplier for multimedia system design 用于多媒体系统设计的可重构低能量倍增器
Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era Pub Date : 2000-04-27 DOI: 10.1109/IWV.2000.844541
Suhwan Kim, M. Papaefthymiou
{"title":"Reconfigurable low energy multiplier for multimedia system design","authors":"Suhwan Kim, M. Papaefthymiou","doi":"10.1109/IWV.2000.844541","DOIUrl":"https://doi.org/10.1109/IWV.2000.844541","url":null,"abstract":"This paper proposes a reconfigurable pipelined multiplier architecture that achieves high performance and very low energy dissipation by adapting its structure to computational requirements over time. In this reconfigurable multiplier energy is saved by disabling and bypassing an appropriate number of pipeline stages whenever input data rates are low. To evaluate the efficiency of our multiplier architecture, we have designed a multiplier-based inverse quantizer (IQ) for MPEG-2 MP@ML. Pipelines are dynamically reconfigured according to the size of the picture and the number of nonzero quantized DCT coefficients per block. In comparison with corresponding multiplier implementations that use conventional pipelines, our reconfigurable multipliers dissipate about 31-58% less energy. Relative energy savings increase with decreasing data rates, since our reconfigurable structures stay in a low energy configuration for proportionately longer time.","PeriodicalId":300014,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era","volume":"336 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131493431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Validation of complex designs through hardware prototyping 通过硬件原型验证复杂设计
Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era Pub Date : 2000-04-27 DOI: 10.1109/IWV.2000.844544
Gil Stoler
{"title":"Validation of complex designs through hardware prototyping","authors":"Gil Stoler","doi":"10.1109/IWV.2000.844544","DOIUrl":"https://doi.org/10.1109/IWV.2000.844544","url":null,"abstract":"Functional validation of complex designs by means of hardware prototyping (emulation) is a major tool used by industry to improve the validation quality at the different chip design program phases. However, fitting a design into emulation is not a simple task. Lots of elements collide in orthogonal domains, while trying to get emulation going. This paper goes through selected topics in ramping up a large emulation program, emphasizing items that worth looking into, in order to render the emulation program feasible and effective. This paper does not involve specific project numbers and statistics. However, it is based on the experience from complex design emulation programs.","PeriodicalId":300014,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131162991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Architectural adaptation in AMRM machines AMRM机器中的架构适应
Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era Pub Date : 2000-04-27 DOI: 10.1109/IWV.2000.844533
Rajesh K. Gupta
{"title":"Architectural adaptation in AMRM machines","authors":"Rajesh K. Gupta","doi":"10.1109/IWV.2000.844533","DOIUrl":"https://doi.org/10.1109/IWV.2000.844533","url":null,"abstract":"Application adaptive architectures use architectural mechanisms and policies to achieve system level performance goals. The AMRM project at UC Irvine focuses on adaptation of the memory hierarchy and its role in latency and bandwidth management. This paper describes the architectural principles and first implementation of the AMRM machine proof-of-concept prototype.","PeriodicalId":300014,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134483244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Dynamic voltage scaling techniques for distributed microsensor networks 分布式微传感器网络的动态电压缩放技术
Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era Pub Date : 2000-04-27 DOI: 10.1109/IWV.2000.844528
R. Min, Travis Furrer, Anantha Chandrakasan
{"title":"Dynamic voltage scaling techniques for distributed microsensor networks","authors":"R. Min, Travis Furrer, Anantha Chandrakasan","doi":"10.1109/IWV.2000.844528","DOIUrl":"https://doi.org/10.1109/IWV.2000.844528","url":null,"abstract":"Distributed microsensor networks promise a versatile and robust platform for remote environment monitoring. Crucial to long system lifetimes for these microsensors are algorithms and protocols that provide the option of trading quality for energy savings. Dynamic voltage scaling on the sensor node's processor enables energy savings from these scalable algorithms. We demonstrate dynamic voltage scaling on the beginnings of a sensor node prototype, which currently consists of a commercial processor, a digitally adjustable DC-DC regulator, and a power-aware operating system.","PeriodicalId":300014,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126217892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 127
On-line error detection in multiplexor based FPGAs 基于多路复用的fpga在线错误检测
Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era Pub Date : 2000-04-27 DOI: 10.1109/IWV.2000.844545
A. Jaekel
{"title":"On-line error detection in multiplexor based FPGAs","authors":"A. Jaekel","doi":"10.1109/IWV.2000.844545","DOIUrl":"https://doi.org/10.1109/IWV.2000.844545","url":null,"abstract":"In this paper we introduce a new method for incorporating on-line error detection capabilities in multiplexor based FPGAs. The advantages, with respect to traditional off-line testing are that there is no need to determine test vectors and no need for storage of the test vectors and correct output responses. We have shown that all single faults in the circuit are detectable using our method. Furthermore, faults in the implementation of the functionality of the circuit can be distinguished from faults in the test circuitry. We have also discussed the detection of multiple faults under two fault models-multiple fault single module (MFSM) and single fault multiple module (SFMM) and analyzed the conditions under which faults can be detected using these models.","PeriodicalId":300014,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126406151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A system-level approach to power/performance optimization in wearable computers 可穿戴计算机中功率/性能优化的系统级方法
Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era Pub Date : 2000-04-27 DOI: 10.1109/IWV.2000.844523
A. Smailagic, D. Reilly, D. Siewiorek
{"title":"A system-level approach to power/performance optimization in wearable computers","authors":"A. Smailagic, D. Reilly, D. Siewiorek","doi":"10.1109/IWV.2000.844523","DOIUrl":"https://doi.org/10.1109/IWV.2000.844523","url":null,"abstract":"The paper describes a system-level design approach to the power and performance of Carnegie Mellon's wearable computers dedicated to speech processing-the Speech Translator Smart Modules. While processor speed and type affect power consumption and performance, memory size and type of secondary storage have a significant influence as well. A system-level approach to power/performance optimization is described that improved the metric of (performance/(weight*volume*power)) by over a factor of 300 through the four generations of wearable computers for speech processing.","PeriodicalId":300014,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127266200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Multiple access caches: Energy implications 多访问缓存:能源影响
Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era Pub Date : 2000-04-27 DOI: 10.1109/IWV.2000.844530
H.S. Kim, N. Vijaykrishnan, M. Kandemir, M. J. Irwin
{"title":"Multiple access caches: Energy implications","authors":"H.S. Kim, N. Vijaykrishnan, M. Kandemir, M. J. Irwin","doi":"10.1109/IWV.2000.844530","DOIUrl":"https://doi.org/10.1109/IWV.2000.844530","url":null,"abstract":"In this paper, we model and evaluate the energy consumption of three different multiple access cache architectures that target the reduction of access latencies of associative caches. Further, we compare their energy consumption with that of traditional direct-mapped and set-associative caches. Among all the cache architectures, the most recently used cache is found to be most energy-efficient for all studied benchmarks and configurations. We also evaluated the influence of compiler optimizations on the energy saving of different cache architectures and find that compiler optimization can significantly reduce the memory system energy across all cache architectures. However, the most aggressive optimizations do not necessarily lead to the most energy-efficient code. We also find that the optimizations always reduce the energy consumed due to instruction accesses for the Mediabench benchmark suite unlike the energy consumed by the data accesses.","PeriodicalId":300014,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era","volume":"433 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116404910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Improved synchronization methodologies for high performance digital systems 高性能数字系统的改进同步方法
Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era Pub Date : 2000-04-27 DOI: 10.1109/IWV.2000.844531
S. Welch, K. Kornegay
{"title":"Improved synchronization methodologies for high performance digital systems","authors":"S. Welch, K. Kornegay","doi":"10.1109/IWV.2000.844531","DOIUrl":"https://doi.org/10.1109/IWV.2000.844531","url":null,"abstract":"Traditional synchronization methodologies have largely concentrated on the use of a global clock signal to maximize the functional integration possible on the chip. Unfortunately, distribution of a low skew clock signal over the entire die at current clock rates is becoming increasingly difficult. By using a combination of architectural design and delay insensitive data encoding, it is possible to ameliorate the inter-patch penalties and take synchronization overhead into account. Extending this architectural modeling, it is also possible to account for other types of overhead, such as those due to Vdd changes between digital regions and analog or RF regions, thus enabling design optimizations for system on a chip applications. Finally, a potential methodology for containing metastability at synchronizer boundaries with relatively low latencies is proposed.","PeriodicalId":300014,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131453216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fine-grain pipelined asynchronous adders for high-speed DSP applications 用于高速DSP应用的细粒度流水线异步加法器
Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era Pub Date : 2000-04-27 DOI: 10.1109/IWV.2000.844538
M. Singh, S. Nowick
{"title":"Fine-grain pipelined asynchronous adders for high-speed DSP applications","authors":"M. Singh, S. Nowick","doi":"10.1109/IWV.2000.844538","DOIUrl":"https://doi.org/10.1109/IWV.2000.844538","url":null,"abstract":"A new asynchronous pipeline scheme (called LP/sub w/), and two new pipelined asynchronous adder implementations, are introduced for high-throughput applications such as DSPs for multimedia processing. The pipeline scheme is targeted to dynamic datapaths. A novelty of the approach is that it uses decoupled control for pull-up and pull-down stacks. The adders are pipelined at the gate-level and achieve very high throughput: 930-1023 million additions per second in a 0.6/spl mu/ CMOS process. These results are expected to scale to several gigaoperations per second in more modern technologies.","PeriodicalId":300014,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era","volume":"421 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123146473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 50
An algorithmic approach to building datapath multipliers using (3,2) counters 使用(3,2)计数器构建数据路径乘数器的算法方法
Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era Pub Date : 2000-04-27 DOI: 10.1109/IWV.2000.844542
H. Al-Twaijry, M. Aloqeely
{"title":"An algorithmic approach to building datapath multipliers using (3,2) counters","authors":"H. Al-Twaijry, M. Aloqeely","doi":"10.1109/IWV.2000.844542","DOIUrl":"https://doi.org/10.1109/IWV.2000.844542","url":null,"abstract":"Traditionally multipliers have been laid out manually, using simple delay models for the counters. However, at deep submicron feature sizes, these delay models do not accurately model the resulting delays. Therefore, an algorithmic approach to the design of the multiplier is required. This paper presents an algorithm that connects the counters of the multiplier, under the constraint of a limited number of available wiring tracks. The algorithm uses an advanced delay model for the (3-2) counter. This delay model includes the incremental delay due to the placement and wiring of the counters. The algorithm has been implemented and the resulting program has been used to compare several designs of an IEEE floating point multiplier using several delay models.","PeriodicalId":300014,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era","volume":"42 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132346869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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